12-17-2009 02:50 AM
I am using ML507 (xc5vfx70t-ff1136-1) board for prototyping a gigabit ethernet design. I have generated the design using Xilinx LogiCore tool and selected SGMII mode (8bit, host interface enabled and MDIO enabled) as phy to FPGA link. The example design generated by the tool is not working properly in hardware. The auto negotiation process between FPGA and external phy (over SGMII link) never completes and the "sync_acq_status_0" signal is not constantly "HIGH" after initial synchronisation cycle completes. I have made the auto negotiation bit in the PMA/PCS layer (Phy layers in Rocket IO) by writing through MDIO bus (again read back the MDIO control register 0 to confirm this). When I tried the timing simulation of the generated core, it also shows that "sync_acq_status_0" signal is not constantly "HIGH" after initial synchronisation cycle completes. I guess this loss of synchronisation is preventing the auto negotiation process to complete.
We have another ML505 board with us and I have tried the same thing on that. The only difference is that xc5vfx70t-ff1136-1 uses GTX primitives and xc5vlx50t-ff1136-1 has GTP primitives.
The same logic described above is working fine in ML505. I was wondering what could be wrong in case of xc5vfx70t-ff1136-1 device. The GTX requires an additional DCM to generate 62.5 MHz clock, but this should not a bottle neck.
Does anybody faced similar problem? Any help/clue would be highly appriciated.
01-12-2010 03:06 AM
do you drive the PHY's reset signal?
Its location is at J14 and it has opposite polarity of the core itself.
Also check the setting of the clock generator circuit (SW6 of the ml507) if 125mhz are generated.
Should be set to 00111010 (left to right).
Pls let us know if it helped.