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Adventurer
Adventurer
10,680 Views
Registered: ‎03-06-2015

Multiple AXI-Quad SPI flash design for microblaze

Hi,

 

I want to use 2 AXI-QUAD SPI IP modules in vivado block design as per my hardware. I am using xc7a200tffg1156-1. I have added 2 spi IP modules and conneted all signals but while placing pins i am getting an error like below

 

"[Place 30-99] Placer failed with error: 'There are more instances than sites for type STARTUP'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure."

 

I want this startup signal in boath spi IP'sbecause from this signal only clock will be generated. How can I resolve this problem

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4 Replies
Xilinx Employee
Xilinx Employee
10,654 Views
Registered: ‎07-23-2012

Re: Multiple AXI-Quad SPI flash design for microblaze

You have to generate two AXI Quad SPI IPs- one with STARTUPE2 inside the core and the other with STARTUPE2 outside the core options.

After this, you should share STARTUPE2 primitive between the two IPs. In case if the desired SCK frequency is different for both IPs then you can't share STARTUPE2 in this case one of the IPs can't use STARTUPE2.
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Adventurer
Adventurer
10,637 Views
Registered: ‎03-06-2015

Re: Multiple AXI-Quad SPI flash design for microblaze

can you please tell me how to generate STARTUPE2 inside the core and outside the core.

 

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Visitor apullin2
Visitor
770 Views
Registered: ‎06-29-2018

Re: Multiple AXI-Quad SPI flash design for microblaze

I ended up here after a google search after getting the same error as the original poster.

But the poster's question on clarification on how to actually implement this fix has gone unanswered for 2 1/2 years.
That's disappointing.

Still, I would like to know how to fix this, as I am having the same error.

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381 Views
Registered: ‎10-12-2017

Re: Multiple AXI-Quad SPI flash design for microblaze

Hi @apullin2

Make sure that you untick the option "Enable STARTUP Primitive" in all the Xilinx SPI cores. Refer to the below diagram that I have rounded with RED. 

STARTUP Primitive is used to interface with the configuration logic of the FPGA.

 

 

Regards,

Hemanth

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IP_Setting.JPG

 

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