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Visitor
Posts: 15
Registered: ‎03-05-2014

Partial False Path (unsafe)

I'm trying to flush out all the CDC issues with my design.  I have one left that shows up only in the CDC clock interaction histogram. 

 

Partial False Path (unsafe) orange.

 

According to UG906:  

"Partial False Path (Unsafe) - Orange This category is identical to Timed (Unusable), except that at least one path from the source clock to the destination clock is ignored due to a false path exception."

 

Well I have not set any false paths for the design - at all or at any level.  But some of the paths in the identified clock crossing boundary are within the tx_fifo, a IP core I generated from Vivado.  I drilled down into the tx_fifo ip files and found two XDCs, and one had false paths:

 

set_false_path -through [get_ports rst] -to [get_pins -hierarchical -filter {NAME =~ *rstblk*/*PRE}]
#set_false_path -through [get_ports rst] -to [get_pins -hierarchical -filter {NAME =~ *rstblk*/*CLR}]
set_false_path -from [get_cells -hierarchical -filter {NAME =~ *rstblk*/*rst_reg_reg[*]}]

 

Is this what is giving me my issue?  The WR side and RD side clocks are, of course the two clocks involved in this clock crossing boundary.  

 

If so, how can I get around this issue?  I would have figured Xilinx would have all the right exceptions in their IP XDCs.

 

Thanks

Visitor
Posts: 15
Registered: ‎03-05-2014

Re: Partial False Path (unsafe)

OK more research and empirical testing.  The FIFOs are ok, they are handled properly as far as constraints.  It was actually a synchronization module that we are using from another company.  Basically the one path needed to be false path'd.

 

 

Highlighted
Teacher
Posts: 9,030
Registered: ‎08-14-2007

Re: Partial False Path (unsafe)

Just to be clear in case anyone else comes up with the same issue, are you saying that from these three lines:

 

set_false_path -through [get_ports rst] -to [get_pins -hierarchical -filter {NAME =~ *rstblk*/*PRE}]
#set_false_path -through [get_ports rst] -to [get_pins -hierarchical -filter {NAME =~ *rstblk*/*CLR}]
set_false_path -from [get_cells -hierarchical -filter {NAME =~ *rstblk*/*rst_reg_reg[*]}]

 

the first line is needed by the IP, and the last line came from another XDC from a synchronization module (the middle line is commented out, but presumably also from the IP's XDC)?

-- Gabor
Visitor
Posts: 15
Registered: ‎03-05-2014

Re: Partial False Path (unsafe)

Hi Gabor.

 

No, all three lines came from the yourfifoname.xdc file that is provided when you generate a fifo.  The second line (at least for vivado 15.4) is natively commented out, but the first and last are not.  So both lines are needed for proper clock interaction.

 

In my case, I didn't understand the Partial False Path (unsafe) flag that the clock crossing histogram was telling me for one instance.  The explanation in the user guide was a little misleading.  What I had to do was assign a false path to the instance in my design of the clock crossing and just know/trust that I was handling it properly.

 

The Xilinx FIFO xdc files are fine, it was the grouping with my own logic instance (fifo's were grouped in the same clock interaction as my logic)that made me question the fifos because I had problems with the fifo xdc files a LONG time ago in 13.4 (the first iteration of vivado).  

 

FWIW:   If anyone ever is doubting of the Xilinx xdc files, I encourage a little empirical experimentation.  Dig down into the xdc files, and see what the result actually is if you do comment out an exception.  You can really see the results on the CDC reports and the clock crossing interaction histogram.  hope this helps.

 

 

Partial False Path (unsafe)