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Adventurer
Adventurer
5,440 Views
Registered: ‎08-24-2008

Problem with using DCM

I am using a DCM to forward my main clock as well as generate a multiplied version of it:

 

wire clk_derived;
 wire clk_original;
 
   
  // DCM instantiation
  dcmused dcmused
  (.CLKIN_IN(i_clk),
   .RST_IN(rst),
   .CLKFX_OUT(clk_derived),
   .CLKIN_IBUFG_OUT(),
   .CLK0_OUT(clk_original),
   .LOCKED_OUT(locked)
   );

 

Here, i_clk is the main clock that is input to the design and it is forwarded as clk_original. clk_derived is the multiplied clock. I am using xc4vfx140-11ff1517

 

ISE14.2 kgives the following warnings during physical synthesis. I have set a period constraint of 20 ns for i_clk and the clk_derived clock is set to be 4 ns.

 

LIT:176 - Clock buffer is designated to drive clock loads. BUFG symbol
   "dcmused/CLK0_BUFG_INST" (output signal=clk_original) has a mix of clock and
   non-clock loads. The non-clock loads are:
   Pin I0 of
   DCM_AUTOCALIBRATION_dcmused/DCM_ADV_INST/dcmused/DCM_ADV_INST/md/_n00001
   Pin I1 of
   DCM_AUTOCALIBRATION_dcmused/DCM_ADV_INST/dcmused/DCM_ADV_INST/md/_n00011
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   DCM_AUTOCALIBRATION_dcmused/DCM_ADV_INST/dcmused/DCM_ADV_INST/CLKOUT is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   DCM_AUTOCALIBRATION_dcmused/DCM_ADV_INST/dcmused/DCM_ADV_INST/cd/CLK<1> is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   DCM_AUTOCALIBRATION_dcmused/DCM_ADV_INST/dcmused/DCM_ADV_INST/cd/CLK<5> is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   DCM_AUTOCALIBRATION_dcmused/DCM_ADV_INST/dcmused/DCM_ADV_INST/cd/CLK<4> is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   DCM_AUTOCALIBRATION_dcmused/DCM_ADV_INST/dcmused/DCM_ADV_INST/cd/CLK<2> is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   DCM_AUTOCALIBRATION_dcmused/DCM_ADV_INST/dcmused/DCM_ADV_INST/cd/CLK<6> is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   DCM_AUTOCALIBRATION_dcmused/DCM_ADV_INST/dcmused/DCM_ADV_INST/cd/CLK<3> is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.

 

After generating these two clocks, I am using them for the datapath after DCM in the usual way of designing using always@ blocks. I am unable to figure out the reason for these warnings. Any help would be greatly appreciated.

 The two clocks drive two different FSMs and their associated datapaths.

 

Thanks!

Sharad

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3 Replies
Adventurer
Adventurer
5,399 Views
Registered: ‎08-24-2008

Re: Problem with using DCM

I found the answer and for the benefit of other users, I am posting it here. The explanation is described here:

 

http://www.xilinx.com/support/answers/21435.htm

 

Scroll down to read the section titled" Warning Messages". However, the entire answer record #21435 is important.

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Xilinx Employee
Xilinx Employee
5,382 Views
Registered: ‎08-14-2012

Re: Problem with using DCM

hi,

 

The message warns you that the global clock buffer drives both clock and non-clock loads. For example, a LUT's input pin.

 

As the message says, clock buffer is designated to drive clock loads. The dedicated routing resource generates low skew and optimal timing.

Please evaluate your design and see if the non-clock loads are necessary. In some circumstances, BUFG's output can drive high fanout reset signals to improve timing.

 

If there's no routing restriction, you can just ignore the message.

 

regards,

saurav

 

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Xilinx Employee
Xilinx Employee
5,380 Views
Registered: ‎08-14-2012

Re: Problem with using DCM

additionally for Phydesignrule372

 

The warning is being issued because one of the clock net xxxx is sourced by a combinatorial logic hence making it a Gated-Clock. Xilinx highly recommends that you use the CLB clock enable pin instead of gated clocks. Gated clocks can cause glitches, increased clock delay, clock skew, and other undesirable effects. Using clock enable saves clock resources, and can improve timing characteristic and analysis of the design. 

Refer to page 60 of the user guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/sim.pdf 

In case you are not finding any issues while generating bitstream or board test, you can safely ignore this warning. If you want to use CE instead, refer to the user guide mentioned above.

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