UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Reply
Highlighted
Visitor
Posts: 3
Registered: ‎10-10-2017

Problems with aurora 64/66 core on Virtex 6

Hello.

I try to implement aurora 64/66 core of version 7.3.

FPGA is xc6vsx475t ff1759 -2.

The development environment is ISE 14.7 x64.

I tried to implement an interface between another FPGA and this. I found out, that on the other side signals "lane_up" are all true, but in virtex 6 they are 0. So, if "lane_up" are 0, then the core can't end reset. Why could it be?

I tried to implement example design of the core. ILA shows strange values, like "lane_up" and "channel_up" both are equal to 1, even when there is no interface on the other side and the LED that must show the same value does not light up. I have problems with setup time too, but this is strange, because in ucf file I changed only LOCs and have commented some ports in top module, because I have no buttons for reset.

The frequency of init_clk is 100 MHz.

Modified ucf and top level and core settings are in attachment.

Moderator
Posts: 2,330
Registered: ‎02-16-2010

Re: Problems with aurora 64/66 core on Virtex 6

If you do not have buttons to apply reset, can you use VIO core to apply them? To ensure proper link up of the IP, you will need to apply the reset and pma_init inputs during startup of the design.

Please report your observations after applying the RESET and PMA_INIT inputs to the core using VIO.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
Visitor
Posts: 3
Registered: ‎10-10-2017

Re: Problems with aurora 64/66 core on Virtex 6

I have added a simple process, that acts like the testbench processes:

 

	do_reset <= async_out_i(0);
	
	rst_proc:process(user_clk_i)
	begin
		if rising_edge(user_clk_i) then
			if do_reset='1' then
				rst_counter <= 0;
			else
				if rst_counter<16 then
					rst_counter <= rst_counter + 1;
				end if;
			end if;
			if rst_counter<5 then
				RESET <= '1';
			else
				RESET <= '0';
			end if;
			if rst_counter<16 then
				PMA_INIT <= '1';
			else
				PMA_INIT <= '0';
			end if;
		end if;
	end process;

 

In chipscope I have set async_out_i as a pushbutton (high).

Before these actions all signals in VIO were 0, and 3 of 4 signals "lane_up" were shown with bidirectional arrow. But, when I had changed the special inner reset signal as 1, the arrows disappeared.

Now signal values are the same, but when I set that inner reset, arrows remain.

Changing async_out_i(0) does not cause any changes.

And before the changes I saw strange values in ILA, but now, when I try to do "trigger immidiate", chipscope says, that there is some problems with clock on ILA, and does not show data.

Problems with aurora 64/66 core on Virtex 6