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Observer jahogan
Observer
6,452 Views
Registered: ‎11-06-2012

SelectMAP x8

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Hello,

I am attempting to perform the configuration status register readback sequence for a V6 device over the SelectMAP x8 interface.  The steps I'm following are outlined in Table 7-1 of UG360.

 

My design uses partial reconfiguration, which works as expected prior to reading the status register.  I am able to read the status register once, but afterwards neither subsequent status reads nor full/partial reconfiguration have any effect.  It's as if the SelectMAP interface is no longer responding to the command inputs. During a second read of the status register, the BUSY signal stays high and no data is available on the data pins.

 

The -g persist:yes flags are set during bitstream generation, so I expect the configuration interface to remain active.

What would cause the configuration interface to become unresponsive after reading the status register?

Thanks,

J

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Observer jahogan
Observer
10,225 Views
Registered: ‎11-06-2012

Re: SelectMAP x8

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I solved the inability to read the status register multiple times by playing around with the clocking.  I found that when changing the interface from read to write, if I followed the sequence

 

deassert CSI_B -> cycle CCLK -> set RDWR_B -> cycle CCLK -> assert CSI_B -> cycle CCLK

 

the data transmission became out of sync by one byte, causing the subsequent desync command to be missed.  It appears that CSI_B and RDWR_B changes are synchronous to the same clock edge, and that changing them on different clock cycles causes a problem.

 

The sequence that worked was:

 

deassert CSI_B -> set RDWR_B -> cycle CCLK -> assert CSI_B

 

Then clock through the DOUT_BUSY latency and the data is available.

 

J

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Observer jahogan
Observer
10,226 Views
Registered: ‎11-06-2012

Re: SelectMAP x8

Jump to solution

I solved the inability to read the status register multiple times by playing around with the clocking.  I found that when changing the interface from read to write, if I followed the sequence

 

deassert CSI_B -> cycle CCLK -> set RDWR_B -> cycle CCLK -> assert CSI_B -> cycle CCLK

 

the data transmission became out of sync by one byte, causing the subsequent desync command to be missed.  It appears that CSI_B and RDWR_B changes are synchronous to the same clock edge, and that changing them on different clock cycles causes a problem.

 

The sequence that worked was:

 

deassert CSI_B -> set RDWR_B -> cycle CCLK -> assert CSI_B

 

Then clock through the DOUT_BUSY latency and the data is available.

 

J

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Newbie zhujf
Newbie
4,715 Views
Registered: ‎06-03-2015

Re: SelectMAP x8

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Hello, J

     I am attempting to perform the configuration status register readback sequence for a V5 device over the SelectMAP x8 interface. The steps I'm following are outlined in Table 7-1 of UG191. The readback clock is 10MHz. But the readback 32bit word is "FFFFFFFF", which is error.  I have read the status register by iMPACT. the status value is correct.  can you give me some suggestion for the problem?

     Thanks for your help

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