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Explorer
Posts: 207
Registered: ‎03-06-2014
Accepted Solution

Simulation of hierarchy design does not work !

Dear all,

 

I am using ISE 14.7 targeting a Virtex-5 FPGA. I wrote a VHDL code for the attached figure containing a clk50MHz module, an LFSR and a pulse counter. 

 

The clk50MHz has an input clock of 100MHz and provides a 50MHz clock at its output to feed the LFSR.

The LFSR is used to generate random pattern as an input pulse for pulse counter module.

The pulse counter measures the period of its input signal (here is the 7th bit of count output in LFSR)

 

While I simulated each module individually in the hierarchy design, their corresponding testbench and the results are very nice and they work !

They problem is when I try to simulate the whole Top module that contains all three sub modules (clk50MHz, LFSR, and pulse counter). As you see in the attached timing diagram, the data_o output goes to UUUUUUUUUUUU state while the pulse counter works very nice. I tried to see the action of submodules in simulation of Top file and I see the LFSR receives the 50MHz clock as its input clock but it does not start counting !!!!

 

It is noticable that I have assigned the DATA_O signal to '0' state at the beginning of testbench but it does not work !!

 

I also attached the design files. Can anybody help me to solve this problem? My case is urgent and I do not know how to solve it ?!! Kind replies and helps are mostly appreciated.

 

Regards,

 

 


Accepted Solutions
Highlighted
Teacher
Posts: 9,030
Registered: ‎08-14-2007

Re: Simulation of hierarchy design does not work !

By adding the UUT to the waveform view, it is apparent that the output of your LFSR module is undefined.  Then adding LFSR to the waveform shows the issue at 100 ns.  In that module, you have an output "count" which comes from the signal "cnt" which in turn is created in a clocked process with a synchronous reset.  This means that in order to be reset, you not only need the "reset" input asserted, but also a rising edge on "clk".  Looking at the waveform, "reset" deasserts at the same time as the first rising edge of "clk".  For simulation, it actually deasserts a delta delay before the rising edge of "clk".  So on the first rising_edge, "reset" is already sampled low.  That means your "cnt" signal remains undefined.  There are a number of ways to overcome this issue.  One would be to create an internal reset signal that stays active for one or more cycles after the clock is running.  This might be easily added to your clk50MHz module.  Another approach is to make simulation match the default behavior of synthesis, which is to initialize all registers to zero unless otherwise specified.  This could be done in your LFSR module signal declarations like:

 

    signal cnt :std_logic_vector (WIDTH-1 downto 0) := (others => '0');

 

Another way would be to use an asynchronous reset in your clocked process.

-- Gabor

View solution in original post

tb_top_module.png

All Replies
Teacher
Posts: 9,030
Registered: ‎08-14-2007

Re: Simulation of hierarchy design does not work !

1) you didn't attach the top module in your archive.

 

2) Your simulation waveform view is only showing the ports of the top level module, not any of the intermediate signals.  It's very hard to debug without looking down at least one level to see where the chain is "broken."

-- Gabor
Explorer
Posts: 207
Registered: ‎03-06-2014

Re: Simulation of hierarchy design does not work !

Dear @gszakacs,

 

Thanks for your reply. Sorry about that. Now, in the attachment you find a full package of modules including the Top.vhd file. It seems weird that a chain is broken ! Do you have any idea?

 

Regards,

 

Highlighted
Teacher
Posts: 9,030
Registered: ‎08-14-2007

Re: Simulation of hierarchy design does not work !

By adding the UUT to the waveform view, it is apparent that the output of your LFSR module is undefined.  Then adding LFSR to the waveform shows the issue at 100 ns.  In that module, you have an output "count" which comes from the signal "cnt" which in turn is created in a clocked process with a synchronous reset.  This means that in order to be reset, you not only need the "reset" input asserted, but also a rising edge on "clk".  Looking at the waveform, "reset" deasserts at the same time as the first rising edge of "clk".  For simulation, it actually deasserts a delta delay before the rising edge of "clk".  So on the first rising_edge, "reset" is already sampled low.  That means your "cnt" signal remains undefined.  There are a number of ways to overcome this issue.  One would be to create an internal reset signal that stays active for one or more cycles after the clock is running.  This might be easily added to your clk50MHz module.  Another approach is to make simulation match the default behavior of synthesis, which is to initialize all registers to zero unless otherwise specified.  This could be done in your LFSR module signal declarations like:

 

    signal cnt :std_logic_vector (WIDTH-1 downto 0) := (others => '0');

 

Another way would be to use an asynchronous reset in your clocked process.

-- Gabor
tb_top_module.png
Explorer
Posts: 207
Registered: ‎03-06-2014

Re: Simulation of hierarchy design does not work !

Dear @gszakacs,

 

Thank you so much for nice explanation. The problem got solved and now the counter counts corrctly ! Bravo !

Simulation of hierarchy design does not work !

Accepted Solution Solved