12-11-2009 09:57 PM
I'm new here so this post may show my ignorance on the subject. Please bear with me because I've been trying to get this thing to work for weeks.
What I want to do: get ethernet communication working between a computer and an Virtex 5 FPGA. I also want to program in VHDL (ie. no burning a processor onto the FPGA and using software). I am using the ml505 board to do this.
To get this accomplished I am using the Tri-mode ethernet MAC provided by xilinx.
So far I am following the directions stated exactly in this document:
In summary what I'm doing:
1: Generating the Tri Mode Ethernet MAC Core Wrapper using the core generator tool
2: running implement.sh to implement the example design
3: programming said example design onto the FPGA
4:setting up an ethernet connection between my computer and FPGA and trying to ping the FPGA (while using wireshark to catch any packets)
When I do all this and try to sniff packets in wireshark, I see nothing. No packets show up either outbound or inbound. I'd like to know how to get the MAC working.
My current OS is Fedora 9 if that makes any difference.
11-18-2010 07:58 AM
I had a similar problem in the past so maybe i can help you
Its always good to reset the phy before start sending or receiving packets, so make sure you have an output port to phy_reset
if im not mistaken, the phy reset is asseted on low, so make sure you cover that too
Hope it helps