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Observer
Posts: 38
Registered: ‎10-16-2010
Accepted Solution

The problem about the new RAM of ML605

Hello,

 

We have bought a new ML605 FPGA board including Virtex-6. Our problem is with the RAM of this board. In fact now we have 3 ML605 in our lab. One these boards include 512 MB Ram. Then we bought another ML605 Board a few years ago, which includes 1GB Ram. Our FPGA design for 512 MB Ram was still working by using the half of the memory by applying the corrections in link below.

https://www.xilinx.com/support/answers/44814.html  

 

Last week we bought a new ML605. But our earlier FPGA design didnt work with new board. Then I realized that our last two ML605 boards both include 1 GB ram but they are slightly different. So, I tried the design by replacing the RAM from one board to other one, then I understood that the problem is with the new RAM with the recently bought FPGA. The new board coming with the RAM (MT4JSF12864HZ-1G4D1 1049 PC3-10600S-9-10-C1) doesnt work with our earlier design, but our design works well with the RAM (MT4JSF12864HZ-1G4D1 1135 PC3-10600S-9-11-C1). As you may see, there is slight difference between RAMs (9-11-C1) and  (9-10-C1), and one writes 1049, the other one doesnt. I would like to know, what could be the reason that our design doesnt work with the new RAM ?  Indeed, I couldnt get information from Micron datasheet about the difference. Do you have an idea how I can solve the problem.

Thank you. 


Accepted Solutions
Observer
Posts: 38
Registered: ‎10-16-2010

Re: The problem about the new RAM of ML605

Ok, the problem is solved. If someone has the same problem, first you should use new MIG (3.92) and check very carefully the example design (example_top.v and example_top.ucf) about top level parameters. The MIG 3.92 gives you correct design but not the correct parameters. Second, you should avoid different way of implementing idelay control (iodelay_ctrl.v) and locking of pll (infrastructure.v), make it as same as example design. The final implementation works with both types of 1GB DDR3. 

View solution in original post


All Replies
Voyager
Posts: 1,732
Registered: ‎06-24-2013

Re: The problem about the new RAM of ML605

Hey @kadirakin85,

 

MT4JSF12864HZ identifies the module type and size (1GB DDR3, 204pin SODIMM).

1G4 specifies the speed grade, which in your case is PC3-10600.

D1 is the revision code (you need to consult the factory for details).

The 9-10-C1 and 9-11-C1 describe the timing details (RAS/CAS latency) where smaller is better.

 

The fact that your design works fine with the slower memory means that you can definitely make it work with the faster memory as well, but obviously timing is off and your design doesn't handle this well.

 

Do you have an idea how I can solve the problem.

Besides the obvious (switching out memory modules) adjusting the timing to work with the new or both memories should be the way to go.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
Observer
Posts: 38
Registered: ‎10-16-2010

Re: The problem about the new RAM of ML605

Indeed buying a RAM that works would be an easier solution. But I am not able to find MT4JSF12864HZ 9-11-C1 in the market. So, I have to find a solution (or maybe Xilinx should find a solution). Do you think how can I ask Xilinx to replace my RAM with MT4JSF12864HZ 9-11-C1 ? 

 

The strange thing is that, ML605 came with test software with flash card, and it successfully completes the DDR3 test with 9-10-C1. I also see that DDR3 initialization works correctly. But my FPGA hardware doesnt work with 9-10-C1.

 

I also used the new MIG to generate the DDR3 interface for my FPGA hardware, still my implementation doesnt work with 9-10-C1. 

 

You have told adjusting the timing could be a solution, what you mean by adjusting the timing ?

 

Best,

 

Kadir

 

Observer
Posts: 38
Registered: ‎10-16-2010

Re: The problem about the new RAM of ML605

Ok, the problem is solved. If someone has the same problem, first you should use new MIG (3.92) and check very carefully the example design (example_top.v and example_top.ucf) about top level parameters. The MIG 3.92 gives you correct design but not the correct parameters. Second, you should avoid different way of implementing idelay control (iodelay_ctrl.v) and locking of pll (infrastructure.v), make it as same as example design. The final implementation works with both types of 1GB DDR3. 

The problem about the new RAM of ML605

Accepted Solution Solved