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Adventurer
Posts: 78
Registered: ‎11-22-2016
Accepted Solution

VHDL Simulation with Aurora - Question

Hello all,

Please find the below VHDL code snippet.  

 

        process (user_clock)
          begin
             if rising_edge (user_clock) then
                if (rx_valid_final = '1' and tx_cntrl = "01") then
                    if ( rx_data_reg_pattern /= rx_data) then
                         err_sig_pattern <= err_sig_pattern + '1';
                   else
                        err_sig_pattern <= err_sig_pattern;
                 end if;
               end if;
            end if;
      end process;

 

Here is the information on the objects used in the above code.

 

 user_clock : in std_logic (100 mhz).

 tx_cntrl       : in std_logic_vector(1 downto 0);

 rx_data : in std_logic_vector (15 downto 0);

 signal rx_valid_final  : std_logic := '0';

 signal  rx_data_reg_pattern : std_logic_vector (15 downto 0) := x"a5a5";

 signal err_sig_pattern : std_logic_vector (7 downto 0) := x"00";

 

Note that rx_valid_final will become '1' after some point of time.

 

As per the code during the posedge of user_clock,  whenever rx_data_reg_pattern is not equal to rx_data, I expect the err_sig_pattern to increase by one.

 

But as per simulation ( vivado 2016.4), err_sig_pattern remains at 0. Why is that?. Please see the attached snap.

 

Note that rx_data comes from Aurora core.

 

At 16,663 ns, we are in the rising edge of user_clock, and rx_valid_final is '1', clearly rx_data_reg_pattern and rx_data doesn't match, but still err_sig_pattern wouldn't increase. Please advice.

 

Thanks,

Manoj.

 

 

snap.PNG

Accepted Solutions
Explorer
Posts: 163
Registered: ‎04-12-2017

Re: VHDL Simulation with Aurora - Question

Hi @manoj_xilinx,

 

rx_valid_final cannot be sampled by the rising_edge where the cursor is located.

 

rx_valid_final is sampled by the edge at approx 16670ns. And when that clock arrives, rx_data and reg_pattern are equal so there is no error, at least there is no error according to the code you wrote.

 

Cheers!

Avi Chami MSc
FPGA Site

View solution in original post


All Replies
Explorer
Posts: 163
Registered: ‎04-12-2017

Re: VHDL Simulation with Aurora - Question

Hi @manoj_xilinx,

 

rx_valid_final cannot be sampled by the rising_edge where the cursor is located.

 

rx_valid_final is sampled by the edge at approx 16670ns. And when that clock arrives, rx_data and reg_pattern are equal so there is no error, at least there is no error according to the code you wrote.

 

Cheers!

Avi Chami MSc
FPGA Site
Adventurer
Posts: 78
Registered: ‎11-22-2016

Re: VHDL Simulation with Aurora - Question

Thanks for your response @a_chami. I understood your point. Appreciate it.

 

Do you mind explaining  a bit more on launch and capture  flop in this scenario?. I would appreciate if you can include a diagram with launch and capture flop. I would like to see how this logic gets implemented.

 

 

Thanks for your time.

Regards,

Manoj

 

Explorer
Posts: 163
Registered: ‎04-12-2017

Re: VHDL Simulation with Aurora - Question

[ Edited ]

Hi @manoj_xilinx,

 

I have to assume that, as you said, the launch flops are part of the Aurora core.

 

The receiving flops (the rx_data bus) are implemented elsewhere, I don't have all your code so I don't know where this is done. In your code snippet the rx_data bus is compared to rx_data_reg_pattern. The code snippet you've shown actually implements the register (flops) of the err_sig_pattern counter.

 

If you want to visualize these points better, opening the synthesized design on the schematic view might come handy.

Hope this helps,

Avi Chami MSc
FPGA Site
Adventurer
Posts: 78
Registered: ‎11-22-2016

Re: VHDL Simulation with Aurora - Question

Thanks @a_chami. Your reply helps.

 

Appreciate your time.

 

Manoj

VHDL Simulation with Aurora - Question

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