We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
Thank you. I have successfully build one.
By the way, when I use $fopen to open a file and use $fdisplay to write data into it.
The file was generated but it's empty.
Why I couldn't see anything in the file?
Below lists a section of code, could anyone tell me anything wrong?
initial // Clock process for clk_i
fd = $fopen("d:\\Xilinx\\work\\test_mem\\prbs16bit.txt","w");
clk_i = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk_i = 1'b1;
Your $fclose statement comes after the forever loop, so it is never
reached. What happens to data written inside the loop depends on
your operating system, but usually data is written out to the file in
blocks. When enough file output is available to fill a block
(again block size is OS dependent) the block is written out to the
file. If you don't run the simulation long enough to fill a
block, the file will be empty. For some operating systems,
closing the simulator will force the $fclose to write out pending data
to the file. Another possible behavior is to leave the file empty
when the simulator is closed. Are you using ModelSim under