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Adventurer
Adventurer
4,471 Views
Registered: ‎03-16-2010

Virtex 6 - "CLKFBOUT_MULT_F set to a value that is outside the valid range"

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I am attempting to generate a bit file for the ML605 board using XPS 11.5. When I add the DDR3 controller, I get this error:

"MMCM_ADV symbol
"physical_group_DDR3_SDRAM/DDR3_SDRAM/mpmc_core_0/gen_v6_ddr3_phy.mpmc_phy_if
_0/u_phy_read/u_phy_rdclk_gen/base_perf/DDR3_SDRAM/DDR3_SDRAM/mpmc_core_0/gen
_v6_ddr3_phy.mpmc_phy_if_0/u_phy_read/u_phy_rdclk_gen/u_mmcm_clk_base" has
attribute CLKFBOUT_MULT_F set to a value that is outside the valid range of 5
to 64."

 

According to "http://www.xilinx.com/support/answers/34564.htm, I should be able to fix this using a manual edit of the 'system.mhs' file. However, in this file, the CLKFBOUT_MULT_F value of the only clock generator in the design begins at 6 and by some tweaking I have increased it to 24 but I still get the error.

 

What am I doing wrong?

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Adventurer
Adventurer
5,467 Views
Registered: ‎03-16-2010

Re: Virtex 6 - "CLKFBOUT_MULT_F set to a value that is outside the valid range"

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The workaround I mentioned should be placed in system.mhs according to the answer I linked. But the only CLKFBOUT_MULT_F in there is 6.0, so that was the point where the 'solution' did not work for me. 

 

I added the line to my 'data/system.ucf' file and it ends up with an error that the constraint can not be found. I found a line in 'synthesis/ddr3_sdram_wrapper_xst.srp' specifying that the multiplier is 2:

Elaborating module <MMCM_ADV(BANDWIDTH="OPTIMIZED",CLKIN1_PERIOD=2.5,CLKIN2_PERIOD=10.0,CLKOUT0_DIVIDE_F=2,CLKOUT1_DIVIDE=10,

CLKOUT2_DIVIDE=10,CLKOUT3_DIVIDE=10,CLKOUT4_DIVIDE=10,CLKOUT5_DIVIDE=10,CLKOUT6_DIVIDE=10,CLKOUT0_PHASE=0.0,CLKOUT1_PHASE=0.0,

CLKOUT2_PHASE=0.0,CLKOUT3_PHASE=0.0,CLKOUT4_PHASE=0.0,CLKOUT5_PHASE=0.0,CLKOUT6_PHASE=0.0,CLKOUT0_DUTY_CYCLE=0.5,

CLKOUT1_DUTY_CYCLE=0.5,CLKOUT2_DUTY_CYCLE=0.5,CLKOUT3_DUTY_CYCLE=0.5,CLKOUT4_DUTY_CYCLE=0.5,CLKOUT5_DUTY_CYCLE=0.5,

CLKOUT6_DUTY_CYCLE=0.5,CLKOUT0_USE_FINE_PS="TRUE",COMPENSATION="INTERNAL",DIVCLK_DIVIDE=1,CLKFBOUT_MULT_F=2,

CLKFBOUT_PHASE=0.0,REF_JITTER1=0.005,REF_JITTER2=0.005)>.

 

 If that is indeed thecore of the problem, did your UCF workaround meant to be changing that value?

 

 Edit:

I've added the following to the 'data/system.ucf' file (also to maintain the 2/1 ratio between multiplier and divider since my first attempt shifted the clock for the DDR3 to 2GHz):

INST "*/u_mmcm_clk_base" CLKFBOUT_MULT_F = 6;
INST "*/u_mmcm_clk_base" DIVCLK_DIVIDE = 3;

 

The bitstream is now proceeding without errors (it seems) so this might have solved the problem for me.

 

Does this mean the DDR3 controller from XPS 11.5 has a bug?

 

Edit: it seems the MMCM itself has the problem and will be fixed in XPS 12.1: http://www.zylinks.com/support/answers/34099.htm

Message Edited by cyberwizzard on 03-20-2010 07:41 AM
Message Edited by cyberwizzard on 03-20-2010 04:27 PM
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Xilinx Employee
Xilinx Employee
4,466 Views
Registered: ‎01-03-2008

Re: Virtex 6 - "CLKFBOUT_MULT_F set to a value that is outside the valid range"

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It isn't clear where you in the design flow you tried to implement the work around.  Try adding the following to your top level UCF file.

 

INST "physical_group_DDR3_SDRAM/DDR3_SDRAM/mpmc_core_0/gen_v6_ddr3_phy.mpmc_phy_if
_0/u_phy_read/u_phy_rdclk_gen/base_perf/DDR3_SDRAM/DDR3_SDRAM/mpmc_core_0/gen
_v6_ddr3_phy.mpmc_phy_if_0/u_phy_read/u_phy_rdclk_gen/u_mmcm_clk_base"  CLKFBOUT_MULT_F = 5;

------Have you tried typing your question into Google? If not you should before posting.
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Adventurer
Adventurer
5,468 Views
Registered: ‎03-16-2010

Re: Virtex 6 - "CLKFBOUT_MULT_F set to a value that is outside the valid range"

Jump to solution

The workaround I mentioned should be placed in system.mhs according to the answer I linked. But the only CLKFBOUT_MULT_F in there is 6.0, so that was the point where the 'solution' did not work for me. 

 

I added the line to my 'data/system.ucf' file and it ends up with an error that the constraint can not be found. I found a line in 'synthesis/ddr3_sdram_wrapper_xst.srp' specifying that the multiplier is 2:

Elaborating module <MMCM_ADV(BANDWIDTH="OPTIMIZED",CLKIN1_PERIOD=2.5,CLKIN2_PERIOD=10.0,CLKOUT0_DIVIDE_F=2,CLKOUT1_DIVIDE=10,

CLKOUT2_DIVIDE=10,CLKOUT3_DIVIDE=10,CLKOUT4_DIVIDE=10,CLKOUT5_DIVIDE=10,CLKOUT6_DIVIDE=10,CLKOUT0_PHASE=0.0,CLKOUT1_PHASE=0.0,

CLKOUT2_PHASE=0.0,CLKOUT3_PHASE=0.0,CLKOUT4_PHASE=0.0,CLKOUT5_PHASE=0.0,CLKOUT6_PHASE=0.0,CLKOUT0_DUTY_CYCLE=0.5,

CLKOUT1_DUTY_CYCLE=0.5,CLKOUT2_DUTY_CYCLE=0.5,CLKOUT3_DUTY_CYCLE=0.5,CLKOUT4_DUTY_CYCLE=0.5,CLKOUT5_DUTY_CYCLE=0.5,

CLKOUT6_DUTY_CYCLE=0.5,CLKOUT0_USE_FINE_PS="TRUE",COMPENSATION="INTERNAL",DIVCLK_DIVIDE=1,CLKFBOUT_MULT_F=2,

CLKFBOUT_PHASE=0.0,REF_JITTER1=0.005,REF_JITTER2=0.005)>.

 

 If that is indeed thecore of the problem, did your UCF workaround meant to be changing that value?

 

 Edit:

I've added the following to the 'data/system.ucf' file (also to maintain the 2/1 ratio between multiplier and divider since my first attempt shifted the clock for the DDR3 to 2GHz):

INST "*/u_mmcm_clk_base" CLKFBOUT_MULT_F = 6;
INST "*/u_mmcm_clk_base" DIVCLK_DIVIDE = 3;

 

The bitstream is now proceeding without errors (it seems) so this might have solved the problem for me.

 

Does this mean the DDR3 controller from XPS 11.5 has a bug?

 

Edit: it seems the MMCM itself has the problem and will be fixed in XPS 12.1: http://www.zylinks.com/support/answers/34099.htm

Message Edited by cyberwizzard on 03-20-2010 07:41 AM
Message Edited by cyberwizzard on 03-20-2010 04:27 PM
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