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Visitor
Posts: 6
Registered: ‎05-16-2013

idelayctrl with iodelay_group example

Hello,

 

can someone please post a simple working constraint script, where one IDELAYCTRL is driving 9 IODELAYs, with each 3 of them in a separate bank (3x3). Target is a virtex-6 chip.

There is the constraint IODELAY_GROUP, but the usage is not exactly clear to me.

In the UG it is said that for each bank I have to make a new Group - but how to assign the single IDELAYCTRL instance for them?

Assigning multiple Groups for one IDELAYCTRL does not work.

 

regards

 

Highlighted
Historian
Posts: 4,540
Registered: ‎01-23-2009

Re: idelayctrl with iodelay_group example

The IODELAY_GROUP is to associate a specific IODELAYCTRL with a bunch of IODELAYs. This is only necessary when there is some reason for the IODELAYCTRL for one bunch of IODELAYs to be different from others. If your goal is to have all IODELAYCTRLs

  - clocked by the same clock (at 200MHz)

  - reset by the same reset signal

  - have only a single combined ready signal

 

then you don't need to specify multiple IODELAY_GROUPs. Simply instantiate one IODELAYCTRL (with no IODELAY_GROUP) and do not set the IODELAY_GROUP of the IODELAYs, and the tool will automatically replicate the one (and only one) IODELAYCTRL into the three required banks.

 

If you did want a different group for each of the three banks then you would

  - instantiate three IODELAYCTRLs each with a different IODELAY_GROUP

  - for each of the three IODELAYs in a particular bank, us the same IODELAY_GROUP as one of the IODELAYCTRLs

    - the three in the same bank must use the same IODELAY_GROUP

 

But again - this isn't necessary most of the time... Just instantiate one IODELAYCTRL with no IODELAY_GROUP.

 

Avrum

Visitor
Posts: 6
Registered: ‎05-16-2013

Re: idelayctrl with iodelay_group example

very good answer, thank you.

Visitor
Posts: 19
Registered: ‎09-18-2013

Re: idelayctrl with iodelay_group example

Avrum,

Does this work in Vivado as well? I've tried leaving the IDELAY & IDELAYCTRL instances both uncontrained, and also associating them with a group, and I cannot get Vivado to accept either one. Here's a snippet from my Verilog where these are being used (the IODELAY_GROUP properties are shown here commented out because I couldn't get them to work):

IBUFDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) IdsRefClk200(.O(refclk200_pre),.I(refclk200_p),.IB(refclk200_n));

 /*(* IODELAY_GROUP = "IODLY_GROUP" *)*/
IDELAYCTRL IdelayCtl(.RDY(),.REFCLK(refclk200_pre), .RST(Reset));

genvar i;

generate
  for(i=2;i<=12;i=i+1) begin:difbit    
    /* IN  LVDS Decoding */
    IBUFDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) Iibuf(.O(dif_in[i]),.I(dif_in_p[i]),.IB(dif_in_n[i]));  

    /* IDELAY for zero-hold time*/
/*    (* IODELAY_GROUP = "IODLY_GROUP" *) */
    IDELAY Idel(.O(dif_in_delayed[i]),.I(dif_in[i]),.C(1'b0),.CE(1'b0),.INC(1'b0),.RST(1'b0))

 

Here are some selected messages from the vivado.log file:

 

INFO: [Synth 8-638] synthesizing module 'hrt_xrc7v1' [/home/otto/prj/HRT/code/fpga/hrt_xrc7.v:6]
INFO: [Synth 8-638] synthesizing module 'IBUFGDS' [/v/sgl-opt/Xilinx2013.2/Vivado/2013.2/scripts/rt/data/unisim_comp.v:6384]
    Parameter CAPACITANCE bound to: DONT_CARE - type: string
    Parameter DIFF_TERM bound to: TRUE - type: string
    Parameter IBUF_DELAY_VALUE bound to: 0 - type: string
    Parameter IBUF_LOW_PWR bound to: TRUE - type: string
    Parameter IOSTANDARD bound to: LVDS_25 - type: string
INFO: [Synth 8-256] done synthesizing module 'IBUFGDS' (1#30) [/v/sgl-opt/Xilinx2013.2/Vivado/2013.2/scripts/rt/data/unisim_comp.v:6384]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/otto/prj/HRT/code/fpga/hrt_xrc7.v:95]
INFO: [Synth 8-638] synthesizing module 'IDELAYCTRL' [/v/sgl-opt/Xilinx2013.2/Vivado/2013.2/scripts/rt/data/unisim_comp.v:7918]
INFO: [Synth 8-256] done synthesizing module 'IDELAYCTRL' (2#30) [/v/sgl-opt/Xilinx2013.2/Vivado/2013.2/scripts/rt/data/unisim_comp.v:7918]
INFO: [Synth 8-638] synthesizing module 'IBUFDS' [/v/sgl-opt/Xilinx2013.2/Vivado/2013.2/scripts/rt/data/unisim_comp.v:6074]
    Parameter CAPACITANCE bound to: DONT_CARE - type: string
    Parameter DIFF_TERM bound to: TRUE - type: string
    Parameter DQS_BIAS bound to: FALSE - type: string
    Parameter IBUF_DELAY_VALUE bound to: 0 - type: string
    Parameter IBUF_LOW_PWR bound to: TRUE - type: string
    Parameter IFD_DELAY_VALUE bound to: AUTO - type: string
    Parameter IOSTANDARD bound to: LVDS_25 - type: string
INFO: [Synth 8-256] done synthesizing module 'IBUFDS' (3#30) [/v/sgl-opt/Xilinx2013.2/Vivado/2013.2/scripts/rt/data/unisim_comp.v:6074]
INFO: [Synth 8-638] synthesizing module 'IDELAY' [/v/sgl-opt/Xilinx2013.2/Vivado/2013.2/scripts/rt/data/unisim_comp.v:7898]
    Parameter IOBDELAY_TYPE bound to: DEFAULT - type: string
    Parameter IOBDELAY_VALUE bound to: 0 - type: integer
INFO: [Synth 8-256] done synthesizing module 'IDELAY' (4#30) [/v/sgl-opt/Xilinx2013.2/Vivado/2013.2/scripts/rt/data/unisim_comp.v:7898]
.....

Phase 1.8 IO Placement/ Clock Placement/ Build Placer Device
ERROR: [Place 30-578] Found un-associated IO delay instances in the design. The list of IO delay instances without an associated IdelayCtrl is as follows:
    difbit[12].Idel
    difbit[3].Idel
    difbit[10].Idel
    difbit[8].Idel
    difbit[4].Idel
    difbit[2].Idel
    difbit[9].Idel
    difbit[7].Idel
    difbit[6].Idel
    difbit[11].Idel
    difbit[5].Idel

Resolution: Please modify the design so every IO delay instance has an associated IdealCtrl instance.
Phase 1.8 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 6d58c733

Time (s): cpu = 00:01:09 ; elapsed = 00:01:08 . Memory (MB): peak = 2898.457 ; gain = 24.012
Phase 1 Placer Initialization | Checksum: 6d58c733

Time (s): cpu = 00:01:09 ; elapsed = 00:01:08 . Memory (MB): peak = 2898.457 ; gain = 24.012
ERROR: [Place 30-99] Placer failed with error: 'Design has un-associated IO delay instances'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Ending Placer Task | Checksum: 6d58c733


Thanks for any feedback you can provide,

Otto

 

 

 

Visitor
Posts: 19
Registered: ‎09-18-2013

Re: idelayctrl with iodelay_group example

I finally got this to work.  I had to route the 200 MHz ref clock through a BUFG primative so that the IDELAYCTRL would not be optimized away.   Driving from a IBUFGDS, or even a IBUFG doesn't work.  Seems only a BUFG does the trick.  I also changed IDELAY to a IDELAYE2.  Not sure if that matters though.

 

-Otto

 

Historian
Posts: 6,501
Registered: ‎02-25-2008

Re: idelayctrl with iodelay_group example


ocaldwell wrote:

I finally got this to work.  I had to route the 200 MHz ref clock through a BUFG primative so that the IDELAYCTRL would not be optimized away.   Driving from a IBUFGDS, or even a IBUFG doesn't work.  Seems only a BUFG does the trick. 

-Otto

 


That's because the REFCLK input is a clock input and can only be driven by a clock net, i.e., a signal driven by a BUFG.

----------------------------Yes, I do this for a living.
Visitor
Posts: 19
Registered: ‎09-18-2013

Re: idelayctrl with iodelay_group example

I see. I had incorrectly assumed IBUFG and IBUFGDS would automatically infer a BUFG as well, since it is a clock input primitive.
Historian
Posts: 6,501
Registered: ‎02-25-2008

Re: idelayctrl with iodelay_group example


ocaldwell wrote:
I see. I had incorrectly assumed IBUFG and IBUFGDS would automatically infer a BUFG as well, since it is a clock input primitive.

Ah, see, that's the rub. The tools SHOULD infer the BUFG.

 

Sounds like a bug.

----------------------------Yes, I do this for a living.

idelayctrl with iodelay_group example