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Visitor
Posts: 8
Registered: ‎08-13-2017

place design error [DRC 23-20] Rule voilation ODELAY

Hi,

I'm using vivado 2016.2 on ubuntu. I got the following error during generation of bit stream. Suggest me how to  resolve this issue.

 

 

Place_design_error.png
Moderator
Posts: 1,637
Registered: ‎01-16-2013

Re: place design error [DRC 23-20] Rule voilation ODELAY

@maganuru,

 

https://forums.xilinx.com/t5/7-Series-FPGAs/Kintex-7-use-of-ODELAY-block/td-p/778388

 

-_Syed

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Visitor
Posts: 8
Registered: ‎08-13-2017

Re: place design error [DRC 23-20] Rule voilation ODELAY

I didnt added any ODELAY component to my design. And I dint understood what "You'll have to re-spin the hardware with a HP bank to sue ODELAY" does this mean ?

Moderator
Posts: 1,637
Registered: ‎01-16-2013

Re: place design error [DRC 23-20] Rule voilation ODELAY

[ Edited ]

@maganuru,


Check DATAOUT pin of ODELAY which should be connected to IOB which I believe are in HR banks. hence the error message. 

"You'll have to re-spin the hardware with a HP bank to sue ODELAY

The suggest you need to change the IO ports to HP bank.

 

Page 134 in below UG:

https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

 

--Syed

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Registered: ‎09-20-2012

Re: place design error [DRC 23-20] Rule voilation ODELAY

Hi @maganuru

 

From the cell name, it looks like the ODELAY cell is inside RGMII IP. As mentioned by other poster, the ODELAY's are available only in HP banks, you will have to lock the ports associated with these ODELAY's to HP IO bank.

Thanks,
Deepika.
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place design error [DRC 23-20] Rule voilation ODELAY