10-10-2017 09:06 AM
i used iodelay1 to delay clock of 400 mhz . in mistake i left signal_pattern attrib as data , instaded of clock.
my design work ok . but is can affect my desigen can you advize
10-10-2017 09:15 AM
This attribute affects the static timing analysis calculation of the variability of the delay on the IDELAY.
When the IDELAY delays a data pattern, the delay through the IDELAY gains a variability based on the number of taps used; this is documented as tIDELAYPAT_JIT, which is either +/-5ps/tap (HIGH_PERFORMANCE=TRUE) or +/-9ps/tap (HIGH_PERFORMANCE=FALSE).
When the IDELAY delays a clock, this pattern dependent jitter is not present. By setting it a DATA on a clock, you are increasing the pessimism of your design - it is harder to close timing (particularly on interfaces). If you are meeting timing with it set to DATA then your design will work properly. The net effect is that the tools will under-report the margin on your interfaces.
If you want to see how much margin you really have, you can simply load the implemented DCP file into Vivado, change the property on the IDELAY, and re-run the report_timing commands (or report_timing_summary or report_datasheet). This will show you the timing of the interfaces with the IDELAY in the right mode without having to re-run synthesis and place and route (and generate a new bitstream).
10-10-2017 09:16 AM
Sorry - you said Virtex-6, which means ISE (not Vivado).
So the last part doesn't apply - you cannot get a new report from ISE without re-running place and route. But, as I mentioned above, you don't need to. If your design passed timing with the IDELAY set to DATA, then it will only be better when it is set to CLOCK.