08-24-2018 12:28 AM
Hi,
On SDaccel, is it possible to have, at the same time, two different host applications that are linked to the same FPGA card and with the same bitstream?
The goal is to have access to design registers through AXI4-lite (SDA AXI-L, OCl AXI-L, BAR1 AXI-L) on FPGA by 2 host applictions (not on the same register address).
Also, do we need to take care of inter-process access for concurrent access? Is it managed at hardware level?
Environnement is AWS F1 cloud (FPGA developer AMI 1.4.0) or on-prem boards, SDaccel version is 2017.4 or 2018.2.
Thanks in advance
Julien
08-26-2018 05:53 PM
This is going to be supported in future release.
For now, you may consider multi-threading.
08-26-2018 05:53 PM
This is going to be supported in future release.
For now, you may consider multi-threading.
08-27-2018 06:09 AM