cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
channinglan
Visitor
Visitor
1,779 Views
Registered: ‎08-21-2017

2017.2 sdaceel + github example "no Hw HAL handle" isssue

Jump to solution

run https://github.com/Xilinx/SDAccel_Examples/tree/master/getting_started/host/helloworld_ocl

 

 

 

3.10.0-514.el7.x86_64
Using built-in specs.
COLLECT_GCC=/opt/Xilinx/SDx/2017.2/Vivado/tps/lnx64/gcc-6.2.0/bin/g++
COLLECT_LTO_WRAPPER=/home/test/share/Xilinx_tool/SDx/2017.2/Vivado/tps/lnx64/gcc-6.2.0/bin/../libexec/gcc/x86_64-pc-linux-gnu/6.2.0/lto-wrapper
Target: x86_64-pc-linux-gnu
Configured with: ../../src/lnx64/configure --prefix=/tools/batonroot/rodin/devkits/lnx64/gcc-6.2.0 --enable-languages=c,c++ --with-ppl=/tools/batonroot/rodin/devkits/lnx64/ppl-0.11 --with-cloog=/tools/batonroot/rodin/devkits/lnx64/cloog-ppl-0.15.11 LDFLAGS=-L/tools/batonroot/rodin/devkits/lnx64/cloog-ppl-0.15.11/lib
Thread model: posix
gcc version 6.2.0 (GCC)
-----------------------------------
make all TARGETS=hw DEVICES=xilinx_kcu1500_4ddr-xpr_4_0
-----------------------------------
mkdir -p xclbin
/opt/Xilinx/SDx/2017.2/bin/xocc -c --xp "param:compiler.preserveHlsOutput=1" --xp "param:compiler.generateExtraRunData=true" -s   -o xclbin/vector_addition.hw.xilinx_kcu1500_4ddr-xpr_4_0.xo -t hw --platform xilinx_kcu1500_4ddr-xpr_4_0 ./src/vector_addition.cl

****** xocc v2017.2_sdx (64-bit)
  **** SW Build 1972098 on Wed Aug 23 11:34:38 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

Attempting to get a license: ap_opencl
Feature available: ap_opencl
INFO: [XOCC 60-585] Compiling for hardware target
INFO: [XOCC 60-895]    Target platform: /opt/Xilinx/SDx/2017.2/platforms/xilinx_kcu1500_4ddr-xpr_4_0/xilinx_kcu1500_4ddr-xpr_4_0.xpfm
INFO: [XOCC 60-423]   Target device: xilinx:kcu1500:4ddr-xpr:4.0
INFO: [XOCC 60-242] Creating kernel: 'vector_add'

===>The following messages were generated while  performing high-level synthesis for kernel: vector_add Log file:/home/test/share/Xilinx/git_example/SDAccel_Examples/getting_started/host/helloworld_ocl/_xocc_compile_vector_addition_vector_addition.hw.xilinx_kcu1500_4ddr-xpr_4_0.dir/impl/kernels/vector_add/vivado_hls.log :
INFO: [XOCC 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [XOCC 204-61] Pipelining loop 'readA'.
INFO: [XOCC 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 3.
INFO: [XOCC 204-61] Pipelining loop 'readB'.
INFO: [XOCC 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 3.
INFO: [XOCC 204-61] Pipelining loop 'vadd_writeC'.
INFO: [XOCC 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 4.
INFO: [XOCC 60-594] Finished kernel compilation
INFO: [XOCC 60-586] Created xclbin/vector_addition.hw.xilinx_kcu1500_4ddr-xpr_4_0.xo
INFO: [XOCC 60-791] Total elapsed time: 0h 0m 40s
mkdir -p xclbin
/opt/Xilinx/SDx/2017.2/bin/xocc -l --xp "param:compiler.preserveHlsOutput=1" --xp "param:compiler.generateExtraRunData=true" -s   -o xclbin/vector_addition.hw.xilinx_kcu1500_4ddr-xpr_4_0.xclbin -t hw --platform xilinx_kcu1500_4ddr-xpr_4_0 xclbin/vector_addition.hw.xilinx_kcu1500_4ddr-xpr_4_0.xo

****** xocc v2017.2_sdx (64-bit)
  **** SW Build 1972098 on Wed Aug 23 11:34:38 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

INFO: [XOCC 60-629] Linking for hardware target
INFO: [XOCC 60-895]    Target platform: /opt/Xilinx/SDx/2017.2/platforms/xilinx_kcu1500_4ddr-xpr_4_0/xilinx_kcu1500_4ddr-xpr_4_0.xpfm
INFO: [XOCC 60-423]   Target device: xilinx:kcu1500:4ddr-xpr:4.0
INFO: [XOCC 60-251]   Hardware accelerator integration...
Creating Vivado project and starting FPGA synthesis.
................................................................................................................................
Finished 1st of 5 tasks (FPGA synthesis). Elapsed time: 00h 23m 10s.
.....................
Finished 2nd of 5 tasks (FPGA logic optimization). Elapsed time: 00h 10m 23s.
...........................
Finished 3rd of 5 tasks (FPGA logic placement). Elapsed time: 00h 15m 56s.
..........................
Finished 4th of 5 tasks (FPGA routing). Elapsed time: 00h 22m 30s.
...
Finished 5th of 5 tasks (FPGA bitstream generation). Elapsed time: 00h 12m 16s.

WARNING: [XOCC 60-732] Link warning: One or more timing paths failed timing targeting 300 MHz for kernel clock 'DATA_CLK'. The frequency is being automatically changed to 270.7 MHz to enable proper functionality
INFO: [XOCC 60-586] Created xclbin/vector_addition.hw.xilinx_kcu1500_4ddr-xpr_4_0.xclbin
INFO: [XOCC 60-791] Total elapsed time: 1h 24m 43s
-----------------------------------
emconfigutil --od . --nd 1  --platform xilinx_kcu1500_4ddr-xpr_4_0
-----------------------------------

****** configutil v2017.2_sdx (64-bit)
  **** SW Build 1972098 on Wed Aug 23 11:34:38 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

INFO: [ConfigUtil 60-895]    Target platform: /opt/Xilinx/SDx/2017.2/platforms/xilinx_kcu1500_4ddr-xpr_4_0/xilinx_kcu1500_4ddr-xpr_4_0.xpfm
emulation configuration file `emconfig.json` is created in ./. directory
-----------------------------------
./host.exe   kernels.hw.xclbin
XCL_EMULATION_MODE=hw
-----------------------------------
Linux:3.10.0-514.el7.x86_64:#1 SMP Tue Nov 22 16:42:41 UTC 2016:x86_64
---
XILINX_OPENCL=""
LD_LIBRARY_PATH="/opt/Xilinx/SDx/2017.2/runtime/lib/x86_64:/opt/Xilinx/SDx/2017.2/lib/lnx64.o"
---
platform Name: Xilinx
Vendor Name : Xilinx
Found Platform
Found Device=xilinx_kcu1500_4ddr-xpr_4_0
XCLBIN File Name: vector_addition
INFO: Importing xclbin/vector_addition.hw.xilinx_kcu1500_4ddr-xpr_4_0.xclbin
Loading: 'xclbin/vector_addition.hw.xilinx_kcu1500_4ddr-xpr_4_0.xclbin'
ERROR: device::load_binary binary target=Bin, no Hw HAL handle
ERROR: No program executable for device
ERROR: buffer (2) is not resident in device (0)
Result =
Error: Result mismatch:
i = 0 CPU result = 42 Device result = 0
TEST FAILED
terminate called after throwing an instance of 'xrt::error'
  what():  event 1 never submitted
*** Error in `./helloworld': malloc(): memory corruption: 0x00007f134b2657c7 ***
terminate called recursively
terminate called recursively
terminate called recursively
Aborted (core dumped)
[root@localhost helloworld_ocl]#

 

0 Kudos
1 Solution

Accepted Solutions
channinglan
Visitor
Visitor
2,346 Views
Registered: ‎08-21-2017

 

I modify to " unset XCL_EMULATION_MODE " is ok

View solution in original post

0 Kudos
3 Replies
graces
Moderator
Moderator
1,754 Views
Registered: ‎07-16-2008

I see the environment variable XCL_EMULATION_MODE is set to hw, which is invalid. This could be caused by TARGETS set to hw.

You can run "make all" to compile the application for execution.

 

 

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
-----------------------------------------------------------------------------------------------------------------------
0 Kudos
channinglan
Visitor
Visitor
1,730 Views
Registered: ‎08-21-2017

I modify to

export XCL_EMULATION_MODE=

 

 

get xclbin is    vector_addition..xilinx_kcu1500_4ddr-xpr_4_0.xclbin

but   "helloworld"  host ap  load vector_addition.hw.xilinx_kcu1500_4ddr-xpr_4_0.xclbin

so I change file name vector_addition..xilinx_kcu1500_4ddr-xpr_4_0.xclbin to vector_addition.hw.xilinx_kcu1500_4ddr-xpr_4_0.xclbin

run is ok

0 Kudos
channinglan
Visitor
Visitor
2,347 Views
Registered: ‎08-21-2017

 

I modify to " unset XCL_EMULATION_MODE " is ok

View solution in original post

0 Kudos