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sud
Participant
Participant
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Registered: ‎09-09-2018

AWS F1 actual FPGA not matching execution with Hw emulation- Debugging

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We have created a custom RTL design for communication with application and also some kind of data processing. We are using SDAccel 2019.1.

We have created some test cases in our application to test if FPGA performs the same way as we intend it to. This is what we could make out after running the few test cases,

1. Communication to FPGA is working correctly as intended.

2. Data processing is not correct. (This works in HW-emulation) 

Our question is how do we debug which part of our logic has a problem?? Normally we can use ILA(for a physical FPGA), but here we are loading the FPGA binary from AFI. 

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sud
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Participant
88 Views
Registered: ‎09-09-2018

The way I solved it was by checking what synthesis was optimizing and there was a problem with a default of a case statement. I could not get the ILA to run(Very complex)

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sud
Participant
Participant
89 Views
Registered: ‎09-09-2018

The way I solved it was by checking what synthesis was optimizing and there was a problem with a default of a case statement. I could not get the ILA to run(Very complex)

View solution in original post

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