cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
320 Views
Registered: ‎05-01-2019

AXI interface, DRAM and random accesses

DRAM is designed as a fine grained random access device, at least at 64B granularity (cache blocks)

AXI Interface on the other hand, suggests us to use burst transfer larger than 2KB. Here we lost the fine-grained access abilities.

Why is this the case (any limitations from AXI protocol or DRAM CTRL), and does this limit FPGA to streaming processing at a fine grained level?

It seems to me it's even hard to build caches using BRAM without compulsory prefetching to provide random access of memory on-chip.

 

Regards,

Chen

0 Kudos
5 Replies
Highlighted
Scholar
Scholar
279 Views
Registered: ‎05-21-2015

@zinechant,

It really depends upon the various AXI implementations.  You can build an AXI implementation that handles random access quite well.  Xilinx's MIG tends to do a good job of handling random accesses, whereas Xilinx's AXI block RAM controller does not.  Xilinx's demonstration slaves are rather poor at handling random accesses, but there are better open source AXI designs you can start from if you would rather.

Dan

Highlighted
Visitor
Visitor
256 Views
Registered: ‎05-01-2019

@dgisselq 

Thanks for the reply. It makes sense.

Just to put things into perspective, could you please verify if my following understanding is correct? The path between DRAM and user design is:

DRAM <-> MIG <-> AXI4 slave <-> User Design (AXI master).

In Vitis flow, MIG and AXI4 slave are generated by Vitis compiler.

I guess you are saying the AXI4 slave generated here is the Xilinx demonstration slave which is poor at handling random accesses. Some better AXI slave should be switched in.

0 Kudos
Highlighted
Scholar
Scholar
238 Views
Registered: ‎05-21-2015

@zinechant,

Not quite.

Only a bus master can initiate a transaction.  Slaves only respond to transaction requests.  Therefore, you can't connect the MIG (a slave) directly to a custom slave.  You will need a bus master to talk to the MIG.  That bus master can be a CPU, such as MicroBlaze, ARM, or any component of your own, or it can be a more complicated DMA of some type.  If you'd like to build an AXI master capable of issuing random access requests, you might find this a good example to start from.  If you'd like to build something capable of issuing burst requests (not random), then you'll want to beware of some of the difficulties of working with the AXI protocol.

The first of those two articles will also show you some of the limitations associated with Xilinx's AXI block RAM controller.

Dan

0 Kudos
Highlighted
Visitor
Visitor
232 Views
Registered: ‎05-01-2019

Thanks a lot!

I am not familiar with MIG. But according to the documentation pg150-ultrascale-memory-ip.pdf, MIG includes an AXI4 slave interface.

Is this AXI4 interface in the MIG the one gets used in the Vitis flow, which you call Xilinx demonstration AXI4 slave and the one that doesn't support random access well?


Regards,
Chen

0 Kudos
Highlighted
Scholar
Scholar
222 Views
Registered: ‎05-21-2015

@zinechant,

No.  The MIG AXI4 slave interface handles random access nicely.

This AXI4-lite slave does notNeither does this AXI slave..  Both are generated by Vivado when you ask it to create a custom AXI4 slave IP for you.  Similarly, if you ask Vivado to create a custom AXI4 master you will also get one that can't handle random accesses very well.  The link I gave you above will do that much better than their example.

Dan