AXI interface with RTL kernel wizard (S_AXI_CONTROL interface)
I'm trying to import an RTL design, using the rtl kernel wizard in Vitis. The design has some AXI master interfaces, and the S_AXI_CONTROL interface, to handle the control signals (created by the wizard). This control interface has all the AXI signals as outputs (and also the control signals like ap_start, ap_done, and ap_idle). Some of these AXI signals are also outputs of my RTL logic. The problem is that when I add the logic, I have errors regarding this output signals, since they are outputs of the control interface and also of my RTL logic.
I don't really understand what the control interface does with the AXI signals (that has as outputs), and how to solve this issue.