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nanjing2002
Adventurer
Adventurer
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Registered: ‎01-25-2014

About the max matrix input of Vitis Library's svd

I find that there is Vitis_Libraries/solver/L2/include/hw/MatrixDecomposition/gesvdj.hpp. What is  the max matrix input that the gesvdj function can support providen the reosurce of FPGA is enough?Thank you in advance.

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guozhenp
Xilinx Employee
Xilinx Employee
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Registered: ‎05-01-2013

If not considering the FPGA utilization or interface bandwidth, there is no limitation of the input

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nanjing2002
Adventurer
Adventurer
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Registered: ‎01-25-2014

Thank you for your reply.

I find the design consume tremendous Block RAM much more than the device.

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