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eryk2303
Contributor
Contributor
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Registered: ‎03-24-2021

Axi Stream Vitis IDE

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Hi,

i wanted to use in a "practice" project in Vitis IDE for the Alveo U50 chip the kernel available at: https://github.com/Xilinx/Vitis_Accel_Examples/blob/master/host/streaming_reg_access/src/increment.cpp, unfortunately at the "Emulation-HW" stage the errors shown in the image below are displayed.

eryk2303_0-1627394712322.png

Emulation-SW was built without errors.

Regards 

Eryk

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randyh
Xilinx Employee
Xilinx Employee
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Registered: ‎01-04-2013

Looking at the Excluded Platforms, you will see xdma is listed as excluded and these are the only available type of U50 platforms:

https://github.com/Xilinx/Vitis_Accel_Examples/blob/master/host/streaming_reg_access/README.rst

This exclusion is enforced by the Makefile, but if you are taking a different approach to build then it will not enforce the platform dependency but will have a problem as you encountered. Maybe look at this example instead: 

https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/cpp_kernels/dataflow_stream

 

 

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randyh
Xilinx Employee
Xilinx Employee
490 Views
Registered: ‎01-04-2013

Looking at the Excluded Platforms, you will see xdma is listed as excluded and these are the only available type of U50 platforms:

https://github.com/Xilinx/Vitis_Accel_Examples/blob/master/host/streaming_reg_access/README.rst

This exclusion is enforced by the Makefile, but if you are taking a different approach to build then it will not enforce the platform dependency but will have a problem as you encountered. Maybe look at this example instead: 

https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/cpp_kernels/dataflow_stream

 

 

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eryk2303
Contributor
Contributor
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Registered: ‎03-24-2021

Hi @randyh,

Thank you for your reply

So, can the AXI Steram communication interface be used in top functions (kernel) in Vitis IDE for Alveo U50?

In this example https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/cpp_kernels/dataflow_stream Axi Stream is not use in top function, (like in this example https://github.com/Xilinx/Vitis_Accel_Examples/blob/master/host/streaming_reg_access/src/increment.cpp)

Regards,

Eryk

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randyh
Xilinx Employee
Xilinx Employee
349 Views
Registered: ‎01-04-2013

Yes, a kernel can use a streaming interface (axis) at the top-level, but it needs to get the streaming data from some other element of the design such as streaming data from one kernel to another for instance. So one kernel could read the global memory, or the host memory, and then stream it to another kernel for example. 

eryk2303
Contributor
Contributor
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Registered: ‎03-24-2021

Hi @randyh,

thank you for your reply.

Can vitis generate DMA or must I write kernel do read from global memory for Alveo U50? 

Regards,

Eryk

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