Build Error: DEBUG_IP_LAYOUT segment (7208) exceed the maximum size of 4096

[leonardo.solis]

Hi,

I am trying to build an FPGA binary from an OpenCL kernel ("Krnl_GA") with SDx-2017.4, but the process fails: "DEBUG_IP_LAYOUT segment (7208) exceed the maximum size of 4096".

Here are the linking options used:

...
INFO: [XOCC 60-586] Created xclbin/Krnl_GA.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.xo
INFO: [XOCC 60-791] Total elapsed time: 0h 29m 58s
mkdir -p xclbin
/opt/cad/xilinx/sdx/SDx/2017.4/bin/xocc -l
--xp "param:compiler.version=31"
--xp "param:compiler.preserveHlsOutput=1" 
--xp "param:compiler.generateExtraRunData=true" 
-s -g -I./ -I../ -I./device  
-o xclbin/Krnl_GA.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.xclbin 
-t hw 
--platform /home/wimi/lvs/DSA_SDACCEL_AWS_VU9P/xilinx_aws-vu9p-f1-04261818_dynamic_5_0/xilinx_aws-vu9p-f1-04261818_dynamic_5_0.xpfm 
xclbin/Krnl_GA.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.xo
...

After a while, it outputs:

...
[02:36:40] Finished 5th of 6 tasks (FPGA routing). Elapsed time: 00h 59m 21s 

[02:36:40] Starting bitstream generation..

INFO: [VPL 60-841] Created output file: ./address_map.xml
INFO: [VPL 60-841] Created output file: ./_new_clk_freq
INFO: [VPL 60-841] Created output file: ./routed.dcp
INFO: [XOCC 60-991] clock name 'clk_extra_b0' (clock ID '0') is being mapped to clock name 'DATA_CLK' in the xclbin
INFO: [XOCC 60-991] clock name 'clk_extra_c0' (clock ID '1') is being mapped to clock name 'KERNEL_CLK' in the xclbin
INFO: [XOCC 60-991] clock name 'clk_main_a0' (clock ID '') is being mapped to clock name 'clk_main_a0' in the xclbin
setting depth of 16 for xcl_pipe_chan_GA2IGL_GG_active
setting depth of 16 for xcl_pipe_chan_GA2IGL_IC_active
...
INFO: [CF2SW 83-2205] Adding clock connections...
INFO: [CF2SW 83-2206] Adding reset connections...
ERROR: [XOCC 60-399] xclbincat failed, please see log file for detail: '/home/wimi/lvs/ocladock-fpga-sdx17_4/ocladock-fpga/ofdock_taskpar_xl/_xocc_link_Krnl_GA.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0_Krnl_GA.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.dir/impl/build/Krnl_GA.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0_xclbincat.log'
ERROR: [XOCC 60-626] Kernel link failed to complete
ERROR: [XOCC 60-703] Failed to finish linking
make[1]: *** [xclbin/Krnl_GA.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.xclbin] Error 1
make[1]: Leaving directory `/home/wimi/lvs/ocladock-fpga-sdx17_4/ocladock-fpga/ofdock_taskpar_xl'
make: *** [hw] Error 2

The contents of the "Krnl_GA.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0_xclbincat.log" log file are:

ERROR: The buffer size for the DEBUG_IP_LAYOUT segment (7208) exceed the maximum size of 4096.

I could not find any information related. What could be causing this?

Any help would be greatly appreciated.

Leo

[hongh]

Hi, @leonardo.solis ,

Could you test the same design in SDx 2018.2?

[leonardo.solis]

Hi @hongh,

I will try v2018.2.

Also I have just notice that as a linking flag for "hw" mode I added "-g". However I read that in ug1023 that this may be used only for sw-emu or hw-emu.

Could this be the reason? I have restarted the build process and waiting ...

[leonardo.solis]

Without -g flag for the hw build it still fails. Will try v2018.2

[hongh · Accepted solution]

Hi, @leonardo.solis ,

In SDx 2018.2, the maximum size of DEBUG_IP_LAYOUT increases from 4K to 64K, it may help to resolve the issue.

[leonardo.solis]

Hi @hongh,

I realized that in my main project folder there was file that had the "debug_ip" configuration. It seems it was automatically created when I enabled the "-lapc" (AXI protocol checkers) and  "spm" (SDx performance monitors) flags a couple of weeks.

Although for this time I disabled such options in my Makefile, the tool was still throwing the DEBUG_IP_LAYOUT error. So, deleting such file solved it.

Anyway, I obtained the same error message in my previous experiment  (having explicitly enabled "lapc" + "spm"). In that case, it was more obvious to get such error because I enabled monitoring on several AXI ports. For another experiment like that I will consider SDx v2018.2 

Many thanks!

Leo