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candycrush
Contributor
Contributor
346 Views
Registered: ‎11-28-2018

Building project make makefile reset

Hello,

I want to use multiple ddr banks for rtl kernel.

I did package rtl kernel for build, but when I build using vitis IDE, it resets makefile so revised makefile and cfg files can't be used.

How can I apply revised makefile for rtl kernel?

Thank u!

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2 Replies
hongh
Moderator
Moderator
341 Views
Registered: ‎11-04-2010

HI, @candycrush ,

The Make file generated by Vitis IDE will be updated automatically when the project is rebuilt.

Please refer to the below discussion and set the memory connection for Kernel in Vitis IDE GUI:

https://forums.xilinx.com/t5/Vitis-Acceleration-SDAccel-SDSoC/How-to-assign-Ports-in-Vitis-to-HBM-Banks/m-p/1152109

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candycrush
Contributor
Contributor
283 Views
Registered: ‎11-28-2018

Thank u for replying!!

I solved by your help.

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