10-28-2020 12:27 AM
I want to use multiple ddr banks for rtl kernel.
I did package rtl kernel for build, but when I build using vitis IDE, it resets makefile so revised makefile and cfg files can't be used.
How can I apply revised makefile for rtl kernel?
10-28-2020 12:45 AM - edited 10-28-2020 12:55 AM
HI, @candycrush ,
The Make file generated by Vitis IDE will be updated automatically when the project is rebuilt.
Please refer to the below discussion and set the memory connection for Kernel in Vitis IDE GUI：