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Observer
Observer
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Registered: ‎03-17-2020

Can't find Microblaze MCS in order to load VITIS application

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Hello, I followed mostly the instructions of Microblaze Quick Start Guide, with a target board incorporating a xc7s15 FPGA. 

Using VIVADO 2019.2 defined a system incorporating Microblaze MCS, GPIO switches, LEDs.

Exported the hardware wrapper including the bitstream as specified. 

Went over to VITIS and opened up the project and then added in some features to the Hello World C language app. Generated binary (ELF?) and then "XILINX > Program FPGA." and after that, right clicked on the VITIS application top level and  Run As… Select Launch on Hardware (System Debugger), then click OK. 

What is the correct sequence to ensure the Microblaze can be detected, and is it necessary to program the FPGA first?

01:06:03 INFO : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
targets -set -filter {jtag_cable_name =~ "Platform Cable USB 00000000000000" && level==0} -index 0
fpga -file C:/Users/Eva/ttllc_xilinx_projects/vitis/hello_world/_ide/bitstream/download.bit
configparams mdm-detect-bscan-mask 2
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
----------------End of Script----------------

01:06:03 ERROR : no targets found with "name =~ "*microblaze*#0" && bscan=="USER2" ". available targets:
1* xc7s15
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Highlighted
Observer
Observer
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Registered: ‎03-17-2020

Hi, I achieved a solution after reading a few older forum articles, and thought it might be useful for other developers using Vivado 2019.2 and VITIS IDE 2019.2.1 to take note, if they haven't already figured it out. I had initially followed the process described in Quick Start Guide: MicroBlaze Soft Processor for Vitis 2019.2 , and without thinking much of it, had chosen Microblaze MCS (barebones) instead of just Microblaze (full system). That effectively left out the vital MDM module for debug functionality.

  1. Take at look at the attached block diagram of the test board (it's based upon Spartan-7 FPGA stand-alone dev board by SEEED Studio Spartan Edge Accelerator, a custom board file [if interested, ask me], and a custom "Hearbeat" module that produces without any programming a 1 Hz signal on any assigned pin to verify that at least, after programming the FPGA, the system has a pulse. 
  2. I have put in a board  interface to provide connections to the AXI UARTLite, which I need for my future application. But the Quick Start Guide actually is written for the specific application of USB-JTAG, and doesn't quite say that, which requires a couple of steps, if you start rolling your own block design, or make an addition/modification to the standard blocks: the MDM must have "enable JTAG UART" enabled, and "USER2" for the value in the pull down ADVANCED  > Specified the JTAG user-defined register used.
  3. Make sure the interrupt for the the UARTs are routed to the CONCAT blockAnd run connection automation frequently. 
  4. Go ahead, generate the HDL wrapper, Synthesize, Implement, Generate bitstream as usual. Export the .XSA file as recommned in the Quick Start Guide. Launch Vitis. I recommend developers be absolutely specific in creating a totally clean directory for project work - I spent a lot of hours figuring out that VITIS project management does not clean up  well if a project components are modified, or I redo them.. 
  5. In VITIS, go ahead and start developing per the Guide, and when you have finished modifying the Hello World application code, do the following with reference to the attached VITIS screenshot: modify the BSP routing for for the stdin/stdout pairs to the most convenient UART you choose - but for the GUIDE you need to select MDM here! and then the Guide process (2nd page) can be followed and it does work after a while. 
  6. Obviously  I don't want the 2-way communication routing through the extra overhead of MDM resources, and the USB-JTAG interface, so I will next select the stdin/stdout to my chosen UARTLite interface to exterior pins, but that is another experiment. All I can say is I am very tired of all of the steps required to get here - if someone is writing a guide, they should include all the notes to the guide! 
  7. Also, the suggestion in the GUIDE for the Run As instructions differed for me, and it's annoying not to get a pop-up or link to know which one to use - but I will get to know this in time. 
  8. At the end, I got output from the JTAG-USB, and all the time the Heartbeat was functional, so I know there is a microprocessor system active in the FPGA. 

 

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vitis BSP editor.JPG
VITIS Run As environment.jpg
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Highlighted
Observer
Observer
86 Views
Registered: ‎03-17-2020
hi, in order to test a Microblaze system download, I implemented with testing a custom IP block, to generate a simple Heartbeat signal, that I included in a block design with a Microblaze MCS core. The I/O of the Microblaze MCS has been connected to external pins on the FPGA that I can access through a USB/TTL converter. When I install the FPGA bitstream and the associate ELF file mb_bootloop_le.elf (using Vivado, or VITIS) it is programmed and the Heartbeat is functional. I then proceed with page 2 of https://www.xilinx.com/support/documentation/quick_start/microblaze-quick-start-guide-vitis.pdf to try to load the compiled Hello World application and get exactly the same error message as before .... ???? ERROR : no targets found with "name =~ "*microblaze*#0" && bscan=="USER2" ". available targets:
1* xc7s15
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Highlighted
Observer
Observer
68 Views
Registered: ‎03-17-2020

Hi, I achieved a solution after reading a few older forum articles, and thought it might be useful for other developers using Vivado 2019.2 and VITIS IDE 2019.2.1 to take note, if they haven't already figured it out. I had initially followed the process described in Quick Start Guide: MicroBlaze Soft Processor for Vitis 2019.2 , and without thinking much of it, had chosen Microblaze MCS (barebones) instead of just Microblaze (full system). That effectively left out the vital MDM module for debug functionality.

  1. Take at look at the attached block diagram of the test board (it's based upon Spartan-7 FPGA stand-alone dev board by SEEED Studio Spartan Edge Accelerator, a custom board file [if interested, ask me], and a custom "Hearbeat" module that produces without any programming a 1 Hz signal on any assigned pin to verify that at least, after programming the FPGA, the system has a pulse. 
  2. I have put in a board  interface to provide connections to the AXI UARTLite, which I need for my future application. But the Quick Start Guide actually is written for the specific application of USB-JTAG, and doesn't quite say that, which requires a couple of steps, if you start rolling your own block design, or make an addition/modification to the standard blocks: the MDM must have "enable JTAG UART" enabled, and "USER2" for the value in the pull down ADVANCED  > Specified the JTAG user-defined register used.
  3. Make sure the interrupt for the the UARTs are routed to the CONCAT blockAnd run connection automation frequently. 
  4. Go ahead, generate the HDL wrapper, Synthesize, Implement, Generate bitstream as usual. Export the .XSA file as recommned in the Quick Start Guide. Launch Vitis. I recommend developers be absolutely specific in creating a totally clean directory for project work - I spent a lot of hours figuring out that VITIS project management does not clean up  well if a project components are modified, or I redo them.. 
  5. In VITIS, go ahead and start developing per the Guide, and when you have finished modifying the Hello World application code, do the following with reference to the attached VITIS screenshot: modify the BSP routing for for the stdin/stdout pairs to the most convenient UART you choose - but for the GUIDE you need to select MDM here! and then the Guide process (2nd page) can be followed and it does work after a while. 
  6. Obviously  I don't want the 2-way communication routing through the extra overhead of MDM resources, and the USB-JTAG interface, so I will next select the stdin/stdout to my chosen UARTLite interface to exterior pins, but that is another experiment. All I can say is I am very tired of all of the steps required to get here - if someone is writing a guide, they should include all the notes to the guide! 
  7. Also, the suggestion in the GUIDE for the Run As instructions differed for me, and it's annoying not to get a pop-up or link to know which one to use - but I will get to know this in time. 
  8. At the end, I got output from the JTAG-USB, and all the time the Heartbeat was functional, so I know there is a microprocessor system active in the FPGA. 

 

View solution in original post

vitis BSP editor.JPG
VITIS Run As environment.jpg
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