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xil_tour
Explorer
Explorer
589 Views
Registered: ‎06-14-2018

Data transfer example, no read no write

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Hi,

When running the vanilla data transfer example with soft/hard simulation, I'm surprised to see that no data is actually transferred:

TEST PASSED
INFO: [SDx-EM 22] [Wall clock time: 15:34, Emulation time: 0.00267726 ms] Data transfer between kernel(s) and global memory(s)
dummy_kernel_1:m_axi_gmem0          RD = 0.000 KB               WR = 0.000 KB        
dummy_kernel_1:m_axi_gmem1          RD = 0.000 KB               WR = 0.000 KB     

The "max memory ports" option is checked.

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hongh
Moderator
Moderator
470 Views
Registered: ‎11-04-2010

Hi, @xil_tour ,

"Data Transfer" example illustrates several ways to use the OpenCL API to transfer data to/from the FPGA.

The "dummy" kernel is not called by the host, so there is no data transferring between global memory and kernel.

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brucey
Xilinx Employee
Xilinx Employee
555 Views
Registered: ‎03-24-2010

This does seem that there's no data transfer between kernel and global memory.

Is it a Xilinx example?

Regards,
brucey
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xil_tour
Explorer
Explorer
523 Views
Registered: ‎06-14-2018

Yes, it's the unmodified "data transfer" example from SDx 2018.2.

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xil_tour
Explorer
Explorer
485 Views
Registered: ‎06-14-2018

Bump.

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hongh
Moderator
Moderator
471 Views
Registered: ‎11-04-2010

Hi, @xil_tour ,

"Data Transfer" example illustrates several ways to use the OpenCL API to transfer data to/from the FPGA.

The "dummy" kernel is not called by the host, so there is no data transferring between global memory and kernel.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

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xil_tour
Explorer
Explorer
458 Views
Registered: ‎06-14-2018

Ok, thanks for your time.

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