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Observer
Observer
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Registered: ‎03-17-2020

Debugging when running VITIS application using System ILA

I am not sure if this is the right forum to post this question, as it involves VITIS, applications, debugging and Vivado all together.

Scenario:

I have prepared a barebones microblaze platform (.XSA) with an AXI IIC and AXI UART - and System ILA define after synthesis and before implementation. I can download the bitstream generated from VIVADO into the FPGA and can see the waveforms of the logic analyzer. I wanted to do that while the VITIS C program application is running, but am confused. I have confirmed the debug / ILA is present and working when only VIVADO is involved. But that is before VITIS, where I have written an application and I would like to see the waveforms (e.g., IIC activity) when the application is running. 

I am using VITIS 2020.1. I can only find a reference of VITIS debugging in documents such as  Debugging Applications and Kernels but that discusses a different set of dialogs that I am seeing when I create a platform project. I am thinking the ILA doesn't get transferred to the VITIS environment, while it shows up in the Vivado very nicely - without the application.

Is there a workflow that allows me (in Vivado) to download the Vitis compiled application? Or in VITIS, to initiate the Vivado logic analyzer module? 

Surely this must be a common interest of FPGA developers ... ?

 

 

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Moderator
Moderator
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Registered: ‎11-04-2010

Please refer to the below link:

https://developer.xilinx.com/en/articles/debugging-your-applications-on-an-alveo-data-center-accelerator-.html

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