cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
jungsun
Visitor
Visitor
292 Views
Registered: ‎06-22-2021

Error occurred during Vitis-Libraries example build

Hi, 

I'm working through the Vitis-Libraries example with Alveo-U250.

I'm trying to test the Eigenvalue Solver(syevj).

First, I changed the matrix size from 4 to 88.

If NCU value was changed from 2 to 4, it succeeded in building it.

However, when changing to 8, an error occurs as below.

jungsun_0-1626314002224.png

==================================================================================================================================================================

input => nw@nw-WS-E900-G4-WS980T:~/project/01_vitisLibraries/Vitis_Libraries/solver/L2/tests/syevj$ make all TARGET=hw DEVICE=xilinx_u250_gen3x16_xdma_3_1_202020_1 HOST_ARCH=x86

 

[21:28:07] Run vpl: Step impl: Failed
[21:28:08] Run vpl: FINISHED. Run Status: impl ERROR

===>The following messages were generated while processing /home/nw/project/01_vitisLibraries/Vitis_Libraries/solver/L2/tests/syevj/build_dir.hw.xilinx_u250_gen3x16_xdma_3_1_202020_1/link/vivado/vpl/prj/prj.runs/impl_1 :
ERROR: [VPL 18-1000] Routing results verification failed due to partially-conflicted nets (Up to first 10 of violated nets): level0_i/level1/level1_i/ulp/kernel_syevj_0_1/inst/syevj_double_88_8_U0/dataA_2D_7_2_U/kernel_syevj_0_syevj_double_88_8_s_dataA_2D_0_0_ram_U/D[0] level0_i/level1/level1_i/ulp/kernel_syevj_0_1/inst/syevj_double_88_8_U0/dataA_2D_7_2_U/kernel_syevj_0_syevj_double_88_8_s_dataA_2D_0_0_ram_U/D[1] level0_i/level1/level1_i/ulp/kernel_syevj_0_1/inst/syevj_double_88_8_U0/dataA_2D_7_2_U/kernel_syevj_0_syevj_double_88_8_s_dataA_2D_0_0_ram_U/D[3] level0_i/level1/level1_i/ulp/kernel_syevj_0_1/inst/syevj_double_88_8_U0/dataA_2D_7_2_U/kernel_syevj_0_syevj_double_88_8_s_dataA_2D_0_0_ram_U/D[4] level0_i/level1/level1_i/ulp/kernel_syevj_0_1/inst/syevj_double_88_8_U0/dataA_2D_7_2_U/kernel_syevj_0_syevj_double_88_8_s_dataA_2D_0_0_ram_U/D[5] level0_i/level1/level1_i/ulp/kernel_syevj_0_1/inst/syevj_double_88_8_U0/dataA_2D_7_2_U/kernel_syevj_0_syevj_double_88_8_s_dataA_2D_0_0_ram_U/D[9] level0_i/level1/level1_i/ulp/kernel_syevj_0_1/inst/syevj_double_88_8_U0/dataA_2D_7_2_U/kernel_syevj_0_syevj_double_88_8_s_dataA_2D_0_0_ram_U/D[8] level0_i/level1/level1_i/ulp/kernel_syevj_0_1/inst/syevj_double_88_8_U0/dataA_2D_7_2_U/kernel_syevj_0_syevj_double_88_8_s_dataA_2D_0_0_ram_U/D[11] level0_i/level1/level1_i/ulp/kernel_syevj_0_1/inst/syevj_double_88_8_U0/dataA_2D_7_2_U/kernel_syevj_0_syevj_double_88_8_s_dataA_2D_0_0_ram_U/D[14] level0_i/level1/level1_i/ulp/kernel_syevj_0_1/inst/syevj_double_88_8_U0/dataA_2D_7_2_U/kernel_syevj_0_syevj_double_88_8_s_dataA_2D_0_0_ram_U/D[15]
ERROR: [VPL 60-773] In '/home/nw/project/01_vitisLibraries/Vitis_Libraries/solver/L2/tests/syevj/build_dir.hw.xilinx_u250_gen3x16_xdma_3_1_202020_1/link/vivado/vpl/runme.log', caught Tcl error: problem implementing dynamic region, impl_1: route_design ERROR, please look at the run log file '/home/nw/project/01_vitisLibraries/Vitis_Libraries/solver/L2/tests/syevj/build_dir.hw.xilinx_u250_gen3x16_xdma_3_1_202020_1/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
WARNING: [VPL 60-732] Link warning: No monitor points found for BD automation.
ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, impl_1: route_design ERROR, please look at the run log file '/home/nw/project/01_vitisLibraries/Vitis_Libraries/solver/L2/tests/syevj/build_dir.hw.xilinx_u250_gen3x16_xdma_3_1_202020_1/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
ERROR: [VPL 60-806] Failed to finish platform linker
INFO: [v++ 60-1442] [21:28:08] Run run_link: Step vpl: Failed
Time (s): cpu = 00:01:40 ; elapsed = 04:54:50 . Memory (MB): peak = 1567.559 ; gain = 0.000 ; free physical = 235384 ; free virtual = 243266
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
INFO: [v++ 60-1653] Closing dispatch client.
make: *** [Makefile:199: build_dir.hw.xilinx_u250_gen3x16_xdma_3_1_202020_1/kernel_syevj.xclbin] Error 1

==================================================================================================================================================================

I attached the  runme.log file.(syevj/build_dir.hw.xilinx_u250_gen3x16_xdma_3_1_202020_1/link/vivado/vpl/prj/prj.runs/impl_1/runme.log')

In this example, is the maximum number of NCUs fixed?

I have to perform the results within 1ms for the 88x88 matrix.

Please tell me the possible way.

Additionally, please explain NCU.

Thanks.

0 Kudos
3 Replies
yangc
Xilinx Employee
Xilinx Employee
224 Views
Registered: ‎02-27-2019

From the log file, it's a congestion issue. You can try multiple banks, put your different interfaces on different banks. https://github.com/Xilinx/Vitis-Tutorials/blob/master/Runtime_and_System_Optimization/Feature_Tutorials/01-mult-ddr-banks/README.md

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
jungsun
Visitor
Visitor
194 Views
Registered: ‎06-22-2021

Thank you for your answer.

I tried as below.

conn_u250.cfg:

[connectivity] 
sp =  kernel_syevj_0_1.dataA:bank0
sp =  kernel_syevj_0_1.dataU:bank1
sp =  kernel_syevj_0_1.sigma:bank2
#slr = kernel_syevj_0_1:SLR0

 description.json:

skip...
    "containers": [
        {
            "accelerators": [
                {
                    "location": "kernel_syevj.cpp", 
                    "frequency": 300.0, 
                    "clflags": "-D KERNEL_NAME=kernel_syevj_0", 
                    "name": "kernel_syevj_0", 
                    "num_compute_units": 1, 
                    "compute_units": [
                        {
                            "name": "kernel_syevj_0_1", 
                            "slr": "SLR0", 
                            "arguments": [
                                {
                                    "name": "dataA", 
                                    "memory": "DDR[0]"
                                }, 
                                {
                                    "name": "dataU", 
                                    "memory": "DDR[1]"
                                }, 
                                {
                                    "name": "sigma", 
                                    "memory": "DDR[2]"
                                }
                            ]
                        }
                    ]
                }
            ], 
            "frequency": 300.0, 
            "name": "kernel_syevj"
        }
    ], 
skip...

 

However, the results are the same as before.(log attached.)

Is there any other solution?

0 Kudos
yangc
Xilinx Employee
Xilinx Employee
165 Views
Registered: ‎02-27-2019

In /home/nw/project/01_vitisLibraries/Vitis_Libraries/solver/L2/tests/syevj/build_dir.hw.xilinx_u250_gen3x16_xdma_3_1_202020_1/link/vivado/vpl/prj  you can open the vivado to check it.

 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos