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Observer
Observer
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Registered: ‎03-27-2018

Fail to run SDAccel examples on kcu1500 board

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Hello,

 

I'm trying to run the kcu1500 board with the example vadd (https://github.com/Xilinx/SDAccel_Examples/tree/master/getting_started/misc/vadd),  I got result like this:

 

 

gg@gg-OptiPlex-9010:~/xilinx/SDx/2017.4/sdaccel_examples/getting_started/misc/vadd_20180813_2$ xocc --list_xdevices
xilinx_kcu1500_dynamic_5_0
xilinx_vcu1525_dynamic_5_0
gg@gg-OptiPlex-9010:~/xilinx/SDx/2017.4/sdaccel_examples/getting_started/misc/vadd_20180813_2$ make all TARGETS=hw DEVICES=xilinx_kcu1500_dynamic_5_0
mkdir -p xclbin
/home/gg/xilinx/SDx/2017.4/bin/xocc -c --xp "param:compiler.preserveHlsOutput=1" --xp "param:compiler.generateExtraRunData=true" -s   -o xclbin/krnl_vadd.hw.xilinx_kcu1500_dynamic_5_0.xo -t hw --platform xilinx_kcu1500_dynamic_5_0 ./src/krnl_vadd.cl

****** xocc v2017.4 (64-bit)
  **** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

Attempting to get a license: ap_opencl
Feature available: ap_opencl
INFO: [XOCC 60-585] Compiling for hardware target
INFO: [XOCC 60-895]    Target platform: /home/gg/xilinx/SDx/2017.4/platforms/xilinx_kcu1500_dynamic_5_0/xilinx_kcu1500_dynamic_5_0.xpfm
INFO: [XOCC 60-423]   Target device: xilinx_kcu1500_dynamic_5_0
INFO: [XOCC 60-242] Creating kernel: 'krnl_vadd'

===>The following messages were generated while  performing high-level synthesis for kernel: krnl_vadd Log file:/home/gg/xilinx/SDx/2017.4/sdaccel_examples/getting_started/misc/vadd_20180813_2/_xocc_compile_krnl_vadd_krnl_vadd.hw.xilinx_kcu1500_dynamic_5_0.dir/impl/kernels/krnl_vadd/vivado_hls.log :
INFO: [XOCC 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [XOCC 204-61] Pipelining loop 'Loop 1.1'.
WARNING: [XOCC 204-69] Unable to schedule 'store' operation (/home/gg/xilinx/SDx/2017.4/sdaccel_examples/getting_started/misc/vadd_20180813_2/src/krnl_vadd.cl:48) of variable 'tmp_13', /home/gg/xilinx/SDx/2017.4/sdaccel_examples/getting_started/misc/vadd_20180813_2/src/krnl_vadd.cl:48 on array 'result' due to limited memory ports. Please consider using a memory core with more ports or partitioning the array 'result'.
INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 8, Depth = 10.
INFO: [XOCC 204-61] Pipelining loop 'Loop 1.2'.
WARNING: [XOCC 204-69] Unable to schedule 'load' operation ('result_load_2', /home/gg/xilinx/SDx/2017.4/sdaccel_examples/getting_started/misc/vadd_20180813_2/src/krnl_vadd.cl:53) on array 'result' due to limited memory ports. Please consider using a memory core with more ports or partitioning the array 'result'.
INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 8, Depth = 11.
INFO: [XOCC 60-594] Finished kernel compilation
INFO: [XOCC 60-586] Created xclbin/krnl_vadd.hw.xilinx_kcu1500_dynamic_5_0.xo
INFO: [XOCC 60-791] Total elapsed time: 0h 0m 51s
mkdir -p xclbin
/home/gg/xilinx/SDx/2017.4/bin/xocc -l --xp "param:compiler.preserveHlsOutput=1" --xp "param:compiler.generateExtraRunData=true" -s   -o xclbin/krnl_vadd.hw.xilinx_kcu1500_dynamic_5_0.xclbin -t hw --platform xilinx_kcu1500_dynamic_5_0 xclbin/krnl_vadd.hw.xilinx_kcu1500_dynamic_5_0.xo

****** xocc v2017.4 (64-bit)
  **** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

INFO: [XOCC 60-629] Linking for hardware target
INFO: [XOCC 60-895]    Target platform: /home/gg/xilinx/SDx/2017.4/platforms/xilinx_kcu1500_dynamic_5_0/xilinx_kcu1500_dynamic_5_0.xpfm
INFO: [XOCC 60-897] Reading --xp value from platform: vivado_prop:run.impl_1.STEPS.OPT_DESIGN.TCL.SDXPOST=/home/gg/xilinx/SDx/2017.4/sdaccel_examples/getting_started/misc/vadd_20180813_2/_xocc_link_krnl_vadd.hw.xilinx_kcu1500_dynamic_5_0_krnl_vadd.hw.xilinx_kcu1500_dynamic_5_0.dir/tcl_hooks/dynamic_postopt.tcl
INFO: [XOCC 60-423]   Target device: xilinx_kcu1500_dynamic_5_0
INFO: [XOCC 60-825] xocc command line options for sdx_link are --xo xclbin/krnl_vadd.hw.xilinx_kcu1500_dynamic_5_0.xo -keep
INFO: [XOCC 60-824] sdx_link command line is sdx_link --xo xclbin/krnl_vadd.hw.xilinx_kcu1500_dynamic_5_0.xo -keep --xpfm /home/gg/xilinx/SDx/2017.4/platforms/xilinx_kcu1500_dynamic_5_0/xilinx_kcu1500_dynamic_5_0.xpfm --target hw --output_dir . --temp_dir .
using /home/gg/xilinx/SDx/2017.4/platforms/xilinx_kcu1500_dynamic_5_0/xilinx_kcu1500_dynamic_5_0.xpfm
extracting xo v3 file /home/gg/xilinx/SDx/2017.4/sdaccel_examples/getting_started/misc/vadd_20180813_2/xclbin/krnl_vadd.hw.xilinx_kcu1500_dynamic_5_0.xo
Creating IP database /home/gg/xilinx/SDx/2017.4/sdaccel_examples/getting_started/misc/vadd_20180813_2/_sds/.cdb/xd_ip_db.xml
processing accelerators: /home/gg/xilinx/SDx/2017.4/sdaccel_examples/getting_started/misc/vadd_20180813_2/iprepo/xilinx_com_hls_krnl_vadd_1_0
ip_dir: /home/gg/xilinx/SDx/2017.4/sdaccel_examples/getting_started/misc/vadd_20180813_2/iprepo/xilinx_com_hls_krnl_vadd_1_0
/home/gg/xilinx/SDx/2017.4/bin/xsltproc --stringparam xpath "spirit:component/spirit:name/text()" /home/gg/xilinx/SDx/2017.4/scripts/xdcc/xpathValueOf.xsl /home/gg/xilinx/SDx/2017.4/sdaccel_examples/getting_started/misc/vadd_20180813_2/iprepo/xilinx_com_hls_krnl_vadd_1_0/component.xml
ip_name: krnl_vadd
Creating apsys_0.xml
/home/gg/xilinx/SDx/2017.4/bin/cfgen: 4: /home/gg/xilinx/SDx/2017.4/bin/cfgen: [[: not found
/home/gg/xilinx/SDx/2017.4/bin/cfgen: 4: /home/gg/xilinx/SDx/2017.4/bin/cfgen: [[: not found
Port Specs:
Kernel Specs:
Pipes:

Creating dr.bd.tcl
/home/gg/xilinx/SDx/2017.4/bin/cf2xd: 4: /home/gg/xilinx/SDx/2017.4/bin/cf2xd: [[: not found
/home/gg/xilinx/SDx/2017.4/bin/cf2xd: 4: /home/gg/xilinx/SDx/2017.4/bin/cf2xd: [[: not found
INFO: [CF2XD 83-2203] Adding accelerator adapters...
INFO: [CF2XD 83-2200] Adding axi_interconnects...
INFO: [CF2XD 83-2201] Adding axi_stream_router for scatter-gather DMAs...
INFO: [CF2XD 83-2202] Adding axi_dwidth_converters...
INFO: [CF2XD 83-2208] Adding bus connections for logical connections...
INFO: [CF2XD 83-2205] Adding clock connections...
INFO: [CF2XD 83-2206] Adding reset connections...
/home/gg/xilinx/SDx/2017.4/bin/cf_xsd: 4: /home/gg/xilinx/SDx/2017.4/bin/cf_xsd: [[: not found
/home/gg/xilinx/SDx/2017.4/bin/cf_xsd: 4: /home/gg/xilinx/SDx/2017.4/bin/cf_xsd: [[: not found
INFO: [XOCC 60-812] xocc command line options for vpl are --xp vivado_prop:run.impl_1.STEPS.OPT_DESIGN.TCL.SDXPOST=/home/gg/xilinx/SDx/2017.4/sdaccel_examples/getting_started/misc/vadd_20180813_2/_xocc_link_krnl_vadd.hw.xilinx_kcu1500_dynamic_5_0_krnl_vadd.hw.xilinx_kcu1500_dynamic_5_0.dir/tcl_hooks/dynamic_postopt.tcl -t hw -f xilinx_kcu1500_dynamic_5_0 --xp vivado_prop:run.__KERNEL__.{STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS}={-directive sdx_optimization_effort_high} --xp param:compiler.enableRunInBitstreamGeneration=1 --xp param:compiler.preserveHlsOutput=1 --xp param:compiler.generateExtraRunData=true -s

****** vpl v2017.4 (64-bit)
  **** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

INFO: [VPL 60-839] Read in kernel information from file 'kernel_info.dat'.
INFO: [VPL 60-895]    Target platform: /home/gg/xilinx/SDx/2017.4/platforms/xilinx_kcu1500_dynamic_5_0/xilinx_kcu1500_dynamic_5_0.xpfm
INFO: [VPL 60-423]   Target device: xilinx_kcu1500_dynamic_5_0
INFO: [VPL 60-251]   Hardware accelerator integration...
Creating Vivado project and starting FPGA synthesis.
[23:10:36] Synthesis is running.
[23:11:36] Synthesis is running.
[23:12:36] Synthesis is running.
[23:13:36] Synthesis is running.
[23:14:36] Synthesis is running.
[23:15:36] Synthesis is running.
[23:16:36] Synthesis is running.
[23:17:36] Synthesis is running.


===>The following messages were generated while  Compiling (top level synthesis checkpoint) dynamic region Log file: /home/gg/xilinx/SDx/2017.4/sdaccel_examples/getting_started/misc/vadd_20180813_2/_xocc_link_krnl_vadd.hw.xilinx_kcu1500_dynamic_5_0_krnl_vadd.hw.xilinx_kcu1500_dynamic_5_0.dir/_vpl/ipi/syn/syn.runs/synth_1/runme.log  :
ERROR: [VPL 36-335] '/home/gg/xilinx/SDx/2017.4/sdaccel_examples/getting_started/misc/vadd_20180813_2/_xocc_link_krnl_vadd.hw.xilinx_kcu1500_dynamic_5_0_krnl_vadd.hw.xilinx_kcu1500_dynamic_5_0.dir/_vpl/ipi/syn/syn.srcs/sources_1/bd/bd/ip/pfm_dynamic_memory_subsystem_0/bd_0/ip/ip_5/bd_d216_interconnect_ddr4_mem00_0.dcp' is not a valid design checkpoint
ERROR: [VPL 60-704] Integration error, One or more synthesis runs failed during dynamic region dcp generation
ERROR: [VPL 60-806] Failed to finish platform linker
ERROR: [XOCC 60-398] vpl failed
ERROR: [XOCC 60-626] Kernel link failed to complete
ERROR: [XOCC 60-703] Failed to finish linking
../../..//utility/rules.mk:128: recipe for target 'xclbin/krnl_vadd.hw.xilinx_kcu1500_dynamic_5_0.xclbin' failed
make: *** [xclbin/krnl_vadd.hw.xilinx_kcu1500_dynamic_5_0.xclbin] Error 1

 

 

Any suggestion? Thank you very much!

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Xilinx Employee
Xilinx Employee
1,030 Views
Registered: ‎07-18-2014

Hi @fpga2017,

As you are trying 2017.4 release, could you please try to download git example for 2017.4 branch and try again?

https://github.com/Xilinx/SDAccel_Examples/tree/2017.4

 

master branch does support the latest Xilinx release (which 2018.2). 

 

-Heera

 

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2 Replies
Xilinx Employee
Xilinx Employee
1,031 Views
Registered: ‎07-18-2014

Hi @fpga2017,

As you are trying 2017.4 release, could you please try to download git example for 2017.4 branch and try again?

https://github.com/Xilinx/SDAccel_Examples/tree/2017.4

 

master branch does support the latest Xilinx release (which 2018.2). 

 

-Heera

 

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Highlighted
Observer
Observer
890 Views
Registered: ‎03-27-2018

I just tried, you are right, that's the point! Thanks.

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