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wjh12345
Observer
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Registered: ‎11-13-2019

Failed to Build the hardware Target for system

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Link warning: No monitor points found for BD automation.
ERROR: [VPL 60-704] Integration error, One or more synthesis runs failed during dynamic region dcp generation
ERROR: [VPL 60-704] Integration error, run 'synth_1' couldn't start because one or more of the prerequisite runs failed
ERROR: [VPL 60-704] Integration error, run 'zc706_base_mmult_1_0_synth_1' failed, please look at the run log file '/home/wjh/Vitis-Tutorials/docs/Pathway3/reference-files/run/_x/link/vivado/vpl/prj/prj.runs/zc706_base_mmult_1_0_synth_1/runme.log' for more information
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
ERROR: [VPL 60-806] Failed to finish platform linker
INFO: [v++ 60-1442] [01:25:04] Run run_link: Step vpl: Failed
Time (s): cpu = 00:00:12 ; elapsed = 00:21:14 . Memory (MB): peak = 683.965 ; gain = 0.000 ; free physical = 214 ; free virtual = 1329
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking

d310c8227f3e4d9aa7c7c2c2983d47f.png
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graces
Moderator
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Registered: ‎07-16-2008

It looks you're targetting zc706_base platform. Please note for this Vitis application acceleration, only Alveo data center platforms are supported. The tutorial uses Alveo U200.

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bchebrol
Xilinx Employee
Xilinx Employee
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Registered: ‎06-04-2018

Hi @wjh12345 ,

Have you tested the design for Emulation Flow(sw_emu and hw_emu)?

Can you share the design where you are facing this issue.

Regards,
Vishnu
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graces
Moderator
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1,135 Views
Registered: ‎07-16-2008

It looks something is wrong with the BD output product generation.

As the error indicates, you may take a look at '/home/wjh/Vitis-Tutorials/docs/Pathway3/reference-files/run/_x/link/vivado/vpl/prj/prj.runs/zc706_base_mmult_1_0_synth_1/runme.log' for more details.

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wjh12345
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Registered: ‎11-13-2019

 

Hello, first of all, thank you for your help.

I have tried the design the design for Emulation Flow(sw_emu and hw_emu)

The compilation didn't go wrong, but the simulation did

I'm using the official example.

https://github.com/Xilinx/Vitis-Tutorials/tree/master/docs/Pathway3/reference-files/src

https://github.com/Xilinx/Vitis-Tutorials/blob/master/docs/Pathway3/BuildingAnApplication.md

https://github.com/Xilinx/Vitis-Tutorials/blob/master/docs/Pathway3/Emulation.md#emulation-configuration-files

The software Emulation error is../src/host.cpp:200 Error calling cl::Program program(context, devices, bins, NULL, &err), error code is: -44

The hardware Emulation error is

ERROR: [SDx-EM 08-0] Failed to connect to device process

The following are screenshots of the software Emulation and the hardware Emulation sw_emusw_emu

 

hw_emu.png
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wjh12345
Observer
Observer
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Registered: ‎11-13-2019

Hello, first of all, thank you for your help.

But I can't find the directory of this file.

 

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graces
Moderator
Moderator
1,112 Views
Registered: ‎07-16-2008

It looks you're targetting zc706_base platform. Please note for this Vitis application acceleration, only Alveo data center platforms are supported. The tutorial uses Alveo U200.

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
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wjh12345
Observer
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Registered: ‎11-13-2019

Thanks for your help. Is my following correct?

Embedded targets must run Linux and XRT to support the Vitis application acceleration development flow.

Does this mean that embedded targets running Linux and XRT can do the same thing on the Vitis application acceleration development platform as the Alveo data center acceleration card

 

 

 

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graces
Moderator
Moderator
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Registered: ‎07-16-2008

I'll leave the embedded development details to embedded expert.

You may take a look at vitis user guide and tutorial on embeded design.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug1400-vitis-embedded.pdf

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug1165-zynq-embedded-design-tutorial.pdf

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wjh12345
Observer
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Registered: ‎11-13-2019
Ok,thank you!
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wjh12345
Observer
Observer
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Registered: ‎11-13-2019

 

Hello, do you have time to answer one more question? Thank you very much!

I used xilinx_u200_xdma_201830_2 platform for hardware simulation this time, and the following error occurred during the hardware link

ERROR: [VPL 17-179] Fork failed: Cannot allocate memory

hw.png

 

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