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a1300012709
Observer
Observer
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Registered: ‎07-11-2016

Failed when placer task

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ERROR:This design requires more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 1155 of such cell types but only 1090 compatible sites are available in the target device.

 

In HLS my design only consumed 972 BRAM_18K, but in placer task, SDSoC showed it need 1155 BRAM_18K.

Where did these extra BRAMs came from?

How can I improve my code to meet the requirement of placer, like port or whether cacheable?(partition factor is minimum now)

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sskalick
Xilinx Employee
Xilinx Employee
8,407 Views
Registered: ‎06-29-2015

Hi a1300012709,

 

Please keep in mind that the functions that you mark for hardware are not the only consumers of resources when you implement a design with SDSoC. In order to actually use those cores that are produced with HLS you have to insert other IPs to communicate and transfer data back and forth. Some of these IPs include DMAs, FIFOs, etc. 

 

One of these IPs is the accelerator adapter core that controls the functions marked for hardware and implemented with HLS. This adapter triggers the start/stop signals of the accelerator and manages the BRAMs and FIFOs that interface with your accelerator. For each BRAM interface that results from arguments on your function, an actual BRAM memory is instantiated for your accelerator to use. If an array is transferred to your function, this data is copied from SW into this BRAM prior to starting your core. This BRAM takes up additional resources. Similarly FIFO interfaces from arguments infer FIFO buffer instantiation in this adapter. 

 

All of these interfacing, management, and control IPs take up additional resources on top of the resources used by the functions you mark for hardware.

 

However, there are ways you can control how much resources are used in the systems generated for your application. For example, you can choose the data mover you wish to use for each argument. If you choose an AXI_FIFO this is one of the smallest IPs in terms of resources used (but also one of the slowest). On the other hand a DMA (either SIMPLE_DMA or SG_DMA) will use many times more resources than the AXI_FIFO (but can be many times faster at transferring data). You can also minimize the resources used by choosing to implement your function with FIFO interfaces and then using the SDS buffer pragma to choose a small buffer depth (ie. 16). This will result in smaller interfacing logic than an equivalent array argument implemented as a BRAM (where the entire array must be stored in BRAM). 

 

However, these choices do have a trade off on performance. So you need to manage your resource utilization carefully to keep the design fitting in your target device, while still achieving your target performance. 

 

Sam

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sskalick
Xilinx Employee
Xilinx Employee
8,408 Views
Registered: ‎06-29-2015

Hi a1300012709,

 

Please keep in mind that the functions that you mark for hardware are not the only consumers of resources when you implement a design with SDSoC. In order to actually use those cores that are produced with HLS you have to insert other IPs to communicate and transfer data back and forth. Some of these IPs include DMAs, FIFOs, etc. 

 

One of these IPs is the accelerator adapter core that controls the functions marked for hardware and implemented with HLS. This adapter triggers the start/stop signals of the accelerator and manages the BRAMs and FIFOs that interface with your accelerator. For each BRAM interface that results from arguments on your function, an actual BRAM memory is instantiated for your accelerator to use. If an array is transferred to your function, this data is copied from SW into this BRAM prior to starting your core. This BRAM takes up additional resources. Similarly FIFO interfaces from arguments infer FIFO buffer instantiation in this adapter. 

 

All of these interfacing, management, and control IPs take up additional resources on top of the resources used by the functions you mark for hardware.

 

However, there are ways you can control how much resources are used in the systems generated for your application. For example, you can choose the data mover you wish to use for each argument. If you choose an AXI_FIFO this is one of the smallest IPs in terms of resources used (but also one of the slowest). On the other hand a DMA (either SIMPLE_DMA or SG_DMA) will use many times more resources than the AXI_FIFO (but can be many times faster at transferring data). You can also minimize the resources used by choosing to implement your function with FIFO interfaces and then using the SDS buffer pragma to choose a small buffer depth (ie. 16). This will result in smaller interfacing logic than an equivalent array argument implemented as a BRAM (where the entire array must be stored in BRAM). 

 

However, these choices do have a trade off on performance. So you need to manage your resource utilization carefully to keep the design fitting in your target device, while still achieving your target performance. 

 

Sam

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a1300012709
Observer
Observer
4,626 Views
Registered: ‎07-11-2016

Hi Sam,

  Thank you for so detailed answers. SDSoC is an excellent tool, but it is difficult to design in deeper degree with C code. And I want to know where Can I find the IP cores you mentioned and how much resouces these cores consumed ?

 

Best regards,

Kagura

 

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sskalick
Xilinx Employee
Xilinx Employee
4,619 Views
Registered: ‎06-29-2015

Hi Kagura,

 

You can find the Vivado IPI project located in your build directory at _sds/p0/ipi probably called something like zc702.xpr . You can open then in Vivado and open the Block Design to see all of the IPs that are inserted in your system. For each IP you see, you can go find the associated data sheet for (ie. AXI Interconnect, DMA, ...) and look at the resource tables there.

 

You could also open the Implemented Design in Vivado and choose Tools -> Report -> Report Utilization to see a report of the resources utilized by each IP. 

 

Sam

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a1300012709
Observer
Observer
4,589 Views
Registered: ‎07-11-2016

Hello, Sam

  Thank you for your help! I think I should learn how to use Vivado and Verilog. :)

Best regards,

Kagura

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