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austinkim
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Registered: ‎09-10-2020

How can I insert "place option" in vitis flow ? (insert -no_bufg_opt)

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Hello.

I am currently getting the following error at high freq 250MHz. (but, 100MHz fine.)

austinkim_0-1614394755887.png

I think bufg has a cause, so I want to apply the no_bufg_opt option.

How can I add the "-no_bufg_opt" option to the place step in vitis flow? (such as v++ link option)

Thank you.

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austinkim
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Registered: ‎09-10-2020

This sentence is fine.

--vivado.prop run.impl_1.{'STEPS.PLACE_DESIGN.ARGS.MORE OPTIONS'}={-no_bufg_opt}

Thank you for your attention and reply.

View solution in original post

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hongh
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Registered: ‎11-04-2010

Please refer to "Using the -vivado and -advanced Options" in the below doc to add options for place_design of VPL.

https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/buildingdevicebinary.html#npr1602449118702

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austinkim
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Registered: ‎09-10-2020

Thank you for your reply.

I don't know how to apply "-no_bufg_opt" in PLACE_DESIGN.
I tried some method, but not worked.

try 1. added option in v++ link.   
--vivado.prop run.impl_1.{STEPS.PLACE_DESIGN.ARGS.MORE OPTIONS}={-no_bufg_opt}    
This command was ERROR.


try 2. used   "v++ --vivado.prop run.impl_1.STEPS.PLACE_DESIGN.TCL.PRE=place_option.xdc"

<place_option.xdc>
place_design -directive Explore -no_bufg_opt

 

"try 2" was working. but, PLACE_DESIGN ran twice.

1st. place_design -directive Explore -no_bufg_opt

2nd. place_design -directive Explore

This command was ERROR, it is because PLACE_DESIGN ran twice.
In 1st step is right. (I want to do 1st step only.)

So, how can I apply "-no_bufg_opt" exactly

Please let me know.
Thank you.

 

 

 

 

 

 

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hongh
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Registered: ‎11-04-2010

What's the error message for "try 1"?

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austinkim
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Registered: ‎09-10-2020

A detailed description of "try 1" is as follows.

austinkim_0-1614585459192.png

--vivado.prop run.impl_1.{STEPS.PLACE_DESIGN.ARGS.MORE OPTIONS}={-no_bufg_opt}

ERROR Message is here.

austinkim_1-1614585555502.png

 

ERROR: [v++ 60-602] Source file does not exist: /user2/austin/vitis_aws/aws-fpga/Vitis/examples/210225_aws_startrek_2x/startrek_mvp/Hardware/OPTIONS}={-no_bufg_opt}
INFO: [v++ 60-1662] Stopping dispatch session having empty uuid.

I don't know why occur this ERROR.

Please check my error and thank you for your reply.

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hongh
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Registered: ‎11-04-2010

Please try the below option:

--vivado.prop "run.impl_1.STEPS.PLACE_DESIGN.ARGS.{MORE OPTIONS}={-no_bufg_opt}"

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austinkim
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Registered: ‎09-10-2020

Ah....   ""  The symbol is very important.

As you mentioned, I added that symbol. 

The error that occurred in the tool has disappeared and is being implemented.
When I confirm that it works, I will press kudo.

Thank you for your reply.

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austinkim
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Registered: ‎09-10-2020

After your guide, I checked another error.

===================== ERROR Message ======================

austinkim_0-1614650790912.png

 

ERROR: [VPL 60-773] In'/user2/austin/vitis_aws/aws-fpga/Vitis/examples/210225_aws_startrek_2x/startrek_mvp/Hardware/binary_container_1.build/link/vivado/vpl/runme.log', caught Tcl error: ERROR: [Common 17-158]'name' can only be specified once.
WARNING: [VPL 60-732] Link warning: INFO: Platform does not require extraction of debug/profile metadata.
ERROR: [VPL 60-704] Integration error, Failed to source Vivado impl properties. The project is'prj'. The internal Vivado impl script is'scripts/_vivado_impl_props.tcl'. The script was generated by VPL. An error stack with function names and arguments may be available in the'vivado.log'.
ERROR: [VPL 60-1328] Vpl run'vpl' failed
ERROR: [VPL 60-806] Failed to finish platform linker
INFO: [v++ 60-1442] [11:02:12] Run run_link: Step vpl: Failed
Time(s): cpu = 00:00:13; elapsed = 00:10:55. Memory (MB): peak = 1436.824; gain = 0.000; free physical = 54775; free virtual = 145671
ERROR: [v++ 60-661] v++ link run'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
INFO: [v++ 60-1653] Closing dispatch client.
make: *** [makefile:82: binary_container_1.xclbin] Error 1

 

in runme.log 

austinkim_1-1614650814396.png

This is my link option

austinkim_2-1614650959961.png

 

 

Please check my error.

 

 

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austinkim
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Registered: ‎09-10-2020

This sentence is fine.

--vivado.prop run.impl_1.{'STEPS.PLACE_DESIGN.ARGS.MORE OPTIONS'}={-no_bufg_opt}

Thank you for your attention and reply.

View solution in original post

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hongh
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Registered: ‎11-04-2010

Sorry for the typo:

--vivado.prop "run.impl_1.{STEPS.PLACE_DESIGN.ARGS.MORE OPTIONS}={-no_bufg_opt}"

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