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Contributor
Contributor
1,817 Views
Registered: ‎05-10-2018

How to fix the ERROR: [BD 5-336] This command cannot be run, as the BD-design is locked?

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I am a newcomer to the SDSoC development environment. Currently, I am learning to use the reVision platform to accelerate the process of video on the website "http://www.wiki.xilinx.com/reVISION+Getting+Started+Guide+2017.4+rev2".According to each step when I downloaded the platform which is given. but gotting the following error information. Please tell me how to solve this problem in the zcu102-rv-ss-2017-4-rev2 platform? Due to the given platform which is not exsit the hardware vivado project, how to run report_ip_status, Thank you very much!

 

===>The following messages were generated while creating FPGA bitstream. Log file:/home/j/Downloads/rvss/bil_fil/Debug/_sds/p0/_vpl/ipi/vivado.log :
ERROR: [VPL 5-336] This command cannot be run, as the BD-design is locked. Locked reason(s):
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
zcu102_rv_ss_v_proc_ss_scaler_0
zcu102_rv_ss_v_mix_0_0
zcu102_rv_ss_v_proc_ss_scaler_1
zcu102_rv_ss_mipi_csi2_rx_subsystem_0_0
zcu102_rv_ss_v_proc_ss_csc_0

ERROR: [VPL 60-341] Hardware accelerator integration failed. Aborting build_system. The following log file is available for debugging '/home/j/Downloads/rvss/bil_fil/Debug/_sds/p0/_vpl/ipi/vivado.log'. Contact your local Xilinx representative and provide the log file for further assistance.
ERROR: [VPL 60-806] Failed to finish platform linker
ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling '/opt/Xilinx/SDx/2017.4/bin/vpl --iprepo /home/j/Downloads/rvss/bil_fil/Debug/_sds/iprepo/repo --iprepo /opt/Xilinx/SDx/2017.4/data/ip/xilinx --platform /home/j/Downloads/zcu102_rv_ss/zcu102_rv_ss.xpfm --temp_dir /home/j/Downloads/rvss/bil_fil/Debug/_sds/p0 --output_dir /home/j/Downloads/rvss/bil_fil/Debug/_sds/p0/vpl --input_file /home/j/Downloads/rvss/bil_fil/Debug/_sds/p0/.xsd/top.bd.tcl --target hw --save_temps --kernels w0_xf_bilateralFilter --webtalk_flag SDSoC --remote_ip_cache /home/j/Downloads/rvss/ip_cache '
sds++ log file saved as /home/j/Downloads/rvss/bil_fil/Debug/_sds/reports/sds.log
ERROR: [SdsCompiler 83-5004] Build failed

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Explorer
Explorer
1,816 Views
Registered: ‎09-19-2017
Hi sharpmddr,

The message has everything you need to know:

Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.

You need to open the Vivado project for your SDSoC platorm in Vivado, open the BD (block design) and run Report -> IP Status. Then upgrade any of the IPs that are necessary.

Sam

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Explorer
Explorer
1,817 Views
Registered: ‎09-19-2017
Hi sharpmddr,

The message has everything you need to know:

Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.

You need to open the Vivado project for your SDSoC platorm in Vivado, open the BD (block design) and run Report -> IP Status. Then upgrade any of the IPs that are necessary.

Sam

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Visitor
Visitor
1,357 Views
Registered: ‎02-01-2019

Hi, it seems not work in vivado by update the IP as below:

revision1.png

After I click "Upgrade Selected", it says that

revision2.png

After OK, it  still get some error in my SDx, which says:

Attempting to get a license: ap_opencl
WARNING: [VPL 17-301] Failed to get a license for 'ap_opencl'. Explanation: The license feature ap_opencl could not be found.
Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ".
Attempting to get a license: ap_sdsoc
Feature available: ap_sdsoc
INFO: [VPL 60-895] Target platform: /home/lishen/deephi/zcu102-rv-ss-2018-2/zcu102_rv_ss/zcu102_rv_ss.xpfm
INFO: [VPL 60-423] Target device: zcu102_rv_ss
INFO: [VPL 60-1032] Extracting DSA to /home/lishen/deephi/sdx_for_deephi/dpucore_zcu102/Debug/_sds/p0/vivado/.local/dsa
INFO: [VPL 60-251] Hardware accelerator integration...
Creating Vivado project and starting FPGA synthesis.

WARNING: [VPL 60-1142] Unabled to read data from '/home/lishen/deephi/sdx_for_deephi/dpucore_zcu102/Debug/_sds/p0/vivado/output/generated_reports.log', generated reports will not be copied.

===>The following messages were generated while creating FPGA bitstream. Log file:/home/lishen/deephi/sdx_for_deephi/dpucore_zcu102/Debug/_sds/p0/vivado/vivado.log :
ERROR: [VPL 17-53] User Exception: Project already exists on disk, please use '-force' option to overwrite:
/home/lishen/deephi/sdx_for_deephi/dpucore_zcu102/Debug/_sds/p0/vivado/prj/prj.sim
ERROR: [VPL 60-773] In '/home/lishen/deephi/sdx_for_deephi/dpucore_zcu102/Debug/_sds/p0/vivado/vivado.log', caught Tcl error: ERROR: [Common 17-53] User Exception: Project already exists on disk, please use '-force' option to overwrite:
ERROR: [VPL 60-704] Integration error, problem rebuilding project prj
ERROR: [VPL 60-806] Failed to finish platform linker
ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling '/opt/Xilinx2018.2/SDx/2018.2/bin/vpl --iprepo /home/lishen/deephi/sdx_for_deephi/dpucore_zcu102/Debug/_sds/iprepo/repo --iprepo /opt/Xilinx2018.2/SDx/2018.2/data/ip/xilinx --platform /home/lishen/deephi/zcu102-rv-ss-2018-2/zcu102_rv_ss/zcu102_rv_ss.xpfm --temp_dir /home/lishen/deephi/sdx_for_deephi/dpucore_zcu102/Debug/_sds/p0 --output_dir /home/lishen/deephi/sdx_for_deephi/dpucore_zcu102/Debug/_sds/p0/vpl --input_file /home/lishen/deephi/sdx_for_deephi/dpucore_zcu102/Debug/_sds/p0/.xsd/top.bd.tcl --target hw --save_temps --kernels dpu_cache_sync:dpu_memcpy:dpu_memset:dpu_set_cmd:dpu_set_init:dpu_set_prof:dpu_set_instraddr:dpu_get_instraddr:dpu_get_prof:dpu_set_reset:dpu_connection:dpu_get_finish:dpu_set_finishclr:dpu_set_start:dpu_set_profen:dpu_set_base:dpu_get_base:dpu_get_escnt:dpu_get_status:dpu_get_interrupt:adapter --webtalk_flag SDSoC --remote_ip_cache /home/lishen/deephi/sdx_for_deephi/ip_cache --xp vivado_prop:run.impl_1.strategy=Congestion_SpreadLogic_high --xp "param:compiler.deleteDefaultReportConfigs=false" '
sds++ log file saved as /home/lishen/deephi/sdx_for_deephi/dpucore_zcu102/Debug/_sds/reports/sds.log
ERROR: [SdsCompiler 83-5004] Build failed

makefile:45: recipe for target 'libdpucore_zcu102.so' failed
make: *** [libdpucore_zcu102.so] Error 1

 

But I get my libdpucore_zcu102.so in my project,  it is very strange and do I solved this IP locked problem? Thank you very much.

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Voyager
Voyager
1,318 Views
Registered: ‎05-30-2018

Hi,

If I understood correctly, you managed to open ther SDx staff in Vivado.

How did you proceed ?

Thanks

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Newbie
Newbie
1,215 Views
Registered: ‎04-26-2019

Hello, I had the same problem and upgraded my locked IPs now after I finish on Vivado, how do I go back to SDsoc, or how do I get my design on the board from vivado? I've never used vivado before

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Visitor
Visitor
1,061 Views
Registered: ‎11-08-2018
hey,brother. Can you tell me how to open the zcu102_rv_ss project in vivado? I know one way is open the ‘prj.xpr’ file in SDx-->project-->release-->_sds-->p0-->and so on, however,in this way,I can't find this file. thanks for help.
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1,048 Views
Registered: ‎10-17-2017

@fadyelgawly , @hcyhanson 

To open the revision platform project, find the zcu102_es2_rv_ss.dsa file. You should be able to find it in this location: 

C:\Xilinx\SDx\2018.2\platforms\zcu102-es2-rv-ss-2018-2\zcu102_es2_rv_ss\hw

This dsa file is nothing but a zip file. Simply change the extension to .zip from .dsa

Extract the contents to a folder. 

Find the prj folder inside the extracted folder: 

zcu102_es2_rv_ss.zip\prj

run rebuild.tcl in vivado. 

This is going to rebuild the revision platform vivado project. 

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