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ea872@csus.edu
Visitor
Visitor
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Registered: ‎07-30-2019

How to force write_bitstream after timing failure

Hello,

I am expecting the design to fail for timing with little slack but i still want to generate bitstream but the SDx tool Errors out during bitstream generation. How can i force the bitstream dispite the timing issue?

Thank you,

Eddie 

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hemangd
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Registered: ‎03-16-2017

Hi ea872@csus.edu , 

What errors are you facing? Provide a snapshot of it. 

Generally, tool does not throw errors on timing violations but warnings or critical warnings. 

Despite, use write_bitstream -force 

 

Regards,
hemangd

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ea872@csus.edu
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Registered: ‎07-30-2019

Hi Hemangd,

for some reason the write_bitstream is failing due to the timing failure.

Not sure what is causing this.

Regards,

Eddie

Screen Shot 2019-08-11 at 11.06.02 PM.pngScreen Shot 2019-08-11 at 11.07.09 PM.png

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hemangd
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Registered: ‎03-16-2017

Hi ea872@csus.edu ,

Have a look into this thread. It may help you. https://forums.xilinx.com/t5/SDSoC-Environment-and-reVISION/SDSoC-timing-error/td-p/913446

 

Regards,
hemangd

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ea872@csus.edu
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Registered: ‎07-30-2019

Hi Hemangd,

I am currently using a Makefile not the GUI interferface, would the fix mentioned in the thread work in my case? Also should i use the implementation or synthesis fix mentioned in the post? Lastly what would be the correct syntax for using this paramater mentioned "parameter: param:compiler.skipTimingCheckAndFrequency Scaling=1". 

I also included the make file i am currently using so you can get a better idea of the method i am using.

Can these options be passed in through through a tcl file for example the sds.tcl file?

Regards,

Eddie 

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