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doonny
Explorer
Explorer
332 Views
Registered: ‎07-28-2013

How to set clock uncertainty in v++ compilation flow ?

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In Vitis HLS, user can set or change the clock uncertainty setting. However, in the v++ acceleration flow,  there is only a clock tolerance option.   So are the two setting the same ? If not, how clock uncertainty is set in the v++ compilation flow ?

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kmorris
Xilinx Employee
Xilinx Employee
235 Views
Registered: ‎01-11-2011

In order to change the uncertainty via v++, you will need to utilize the --hls.pre_tcl option with the appropriate command in the file. Documentation is here, and it would look similar to the following:

v++ --hls.pre_tcl ./runPre.tcl

The runPre.tcl file would contain:

set_clock_uncertainty 0.5
-------------------------------------------------------------------------
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-------------------------------------------------------------------------

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kmorris
Xilinx Employee
Xilinx Employee
236 Views
Registered: ‎01-11-2011

In order to change the uncertainty via v++, you will need to utilize the --hls.pre_tcl option with the appropriate command in the file. Documentation is here, and it would look similar to the following:

v++ --hls.pre_tcl ./runPre.tcl

The runPre.tcl file would contain:

set_clock_uncertainty 0.5
-------------------------------------------------------------------------
Please don’t forget to reply, kudo, and accept as solution!
-------------------------------------------------------------------------

View solution in original post