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skaupper
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Registered: ‎10-02-2019

Integrating SDSoC with an already big Design

Hi everyone,

 

I am currently evaluating SDSoC for accelerating some SW components while holding on to our already pretty big FPGA design.

The workflow that I figured would allow us to integrate accelerated SW cores would be the following:

  1. Building the current system using the established scripted workflow.
  2. Exporting the DSA in order to create a SDSoC platform out of it.
  3. Use the platform project as a target for the accelerated applications.

Pretty much what the docs say so far, but I wonder what increase in build time I have to expect from that approach. In order to generate the DSA I have to generate a bitstream, which already takes more than an hour, but when building the SDSoC application the tools have to integrate even further components which trigger yet another implementation run at the very least.

Assuming that the underlying design will change more frequently than the SDSoC applications, what increase in build time should I expect approximately? Am I missing something? Is this even a good application for SDSoC given that FPGA design is changing so frequently?

 

Thanks in advance for any thoughts.

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