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Observer
Observer
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Registered: ‎06-18-2018

Interpret output of hardware emulation

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Hello!

Could you please describe, what output of hardware emulation in SDAccel environment mean and why it runs so long?

INFO: [SDx-EM 22] [Wall clock time: 11:46, Emulation time: 1.54685 ms] Data transfer between kernel(s) and global memory(s)
BANK0          RD = 3.750 KB               WR = 262.812 KB      
BANK1          RD = 0.000 KB               WR = 0.000 KB        
BANK2          RD = 0.000 KB               WR = 0.000 KB        
BANK3          RD = 0.000 KB               WR = 0.000 KB        

INFO: [SDx-EM 22] [Wall clock time: 11:51, Emulation time: 1.73858 ms] Data transfer between kernel(s) and global memory(s)
BANK0          RD = 4.250 KB               WR = 295.438 KB      
BANK1          RD = 0.000 KB               WR = 0.000 KB        
BANK2          RD = 0.000 KB               WR = 0.000 KB        
BANK3          RD = 0.000 KB               WR = 0.000 KB 

 

Each such bunch of four lines - means one launch of the kernel code or one predefined bunch of memory transfer or something else? I am pretty sure that hardware emulation is slower than real because of statistics or something like that? Is it true or there are some other reasons. And also what these Emulation time: 1.73858 ms relates to? Definitely I am waiting more than 2 ms for this output.

 

This is a basic stuff but this output is not described anywhere and I want to be sure that I understand what it shows.

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Moderator
Moderator
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Registered: ‎01-16-2013

Re: Interpret output of hardware emulation

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@skotti,

 

Check this link and see if it helps:

https://forums.xilinx.com/t5/SDAccel/what-does-it-mean-by-the-msg-of-INFO-SDx-EM-22/td-p/785735

 

--Syed

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Highlighted
Moderator
Moderator
783 Views
Registered: ‎01-16-2013

Re: Interpret output of hardware emulation

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@skotti,

 

Check this link and see if it helps:

https://forums.xilinx.com/t5/SDAccel/what-does-it-mean-by-the-msg-of-INFO-SDx-EM-22/td-p/785735

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post