10-15-2020 12:06 AM
I want to make supported MIG IP as RTL kernel using vitis, because I should use a kernel(module) that output read/write command which is MIG IP's input
But as far as I know, Vitis automatically did MIG's role for kernel.
So I think there is no problem making MIG IP as kernel but there is a operation problem of duplicate operation (one is MIG operation, other is Vitis automatic memory operation).
Is there any method to prevent duplicate operation?
10-22-2020 11:33 PM - edited 10-22-2020 11:35 PM
Thank you for reply!
Is there any document to refer to learn how to change AXI PFM properties for it?
10-23-2020 01:35 AM
I discuss the PFM properties in the blog series here:
By default, it will be MIG. you just need to select the AXI PORT