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candycrush
Contributor
Contributor
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Registered: ‎11-28-2018

Is it okay to make supported MIG IP to be RTL kernel using vitis?

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Hello,

I want to make supported MIG IP as RTL kernel using vitis, because I should use a kernel(module) that output read/write command which is MIG IP's input

But as far as I know, Vitis automatically did MIG's role for kernel.

So I think there is no problem making MIG IP as kernel but there is a operation problem of duplicate operation (one is MIG operation, other is Vitis automatic memory operation).

Is there any method to prevent duplicate operation?

 

Thank you!

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stephenm
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Registered: ‎09-12-2007

You would need to do this via the AXI PFM properties in your Vivado design using the sptags. This will then use the MIG

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stephenm
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Registered: ‎09-12-2007

You would need to do this via the AXI PFM properties in your Vivado design using the sptags. This will then use the MIG

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candycrush
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Registered: ‎11-28-2018

Thank you for reply!

Is there any document to refer to learn how to change AXI PFM properties for it?

Thank u!

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stephenm
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Registered: ‎09-12-2007

I discuss the PFM properties in the blog series here:

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Creating-an-Acceleration-Platform-for-Vitis-Part-One-Creating/ba-p/1138208

By default, it will be MIG. you just need to select the AXI PORT

candycrush
Contributor
Contributor
480 Views
Registered: ‎11-28-2018

Oh I see it now, sorry.

And thank u a lot!

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