Meet the Vitis Experts Day : Concluded

[sandrao]

Online Meet the Vitis Experts Day,

Thank you for the questions on the Meet The Experts day on the Vitis Acceleration board. 

We have now finished our 2 sessions thank you to the Experts. 

If there are ideas for other Blogs that our Experts can create to help with your Vitis journey please let us know.

[sandrao]

One question that often gets ask is what is a Vitis Platform? 

[sandrao]

From @ahal 

Hello,

I'm interested  in the Zynq UltraScale+ MPSoc (or better). My goal is to accelerate a piece of c++ software that I have. Have seen the Alveo accelerator card, but don't really understand how the acceleration is achieved, dont know which product to choose (with shortest time too market and best acceleration) 

I have a background in SW, but know absolutely nothing of hardware.

My main question is, before I embark into this world of embedded platforms:

Q1. Will my software run faster and more deterministically when embedded or is it best to just leave it running on my linux server?

Q2. Which of these two platform is best suited for the acceleration job (without the usual fpga vhdl/verilog dev stuff)?

apologies for this very newbie question, but couldn't find an answer elsewhere.

Cheers

https://forums.xilinx.com/t5/Vitis-Acceleration-SDAccel-SDSoC/SW-Acceleration-Embedded-vs-non-embedded-performance/td-p/1149887

[nutang]

Vitis Platform provides developers an environment to create applications for the target boards. 

It consists of hardware component and software component.

- Hardware Component  is an XSA generated from Vivado

- Software Component - boot components generated from a petalinux project for a particular target

Embedded platforms can be customized as per user's requirement and this blog provides a step by step guide to create your own custom platform https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Creating-an-Acceleration-Platform-for-Vitis-Part-One-Creating/ba-p/1138208

[stephenm]

@ahal This is a great question. So, the Vitis IDE is a unified tool that covers multiple market segments such as the Data Center, Automotive, Comms, ect.

For Data Center, the Alveo would be more typically used. This would plug into an X86 server rack, user would use the platform delivered with Vitis to create their accellerated design (kernels), and use the XRT to execute this. 

For Edge users. Deploying on an embedded system such as Zynq or Zynq Ultrascale users can create a custom platform Platform (or use an existing platform) to accelerate their design. For edge platforms, users will need to create the SW and HW components and this is covered in the blog series here:

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Creating-an-Acceleration-Platform-for-Vitis-Part-One-Creating/ba-p/1138208

Your SW would be typically faster on Alveo as the chipset would typically be faster. 

So, the platform would depend on your use-case. 

[sandrao]

@stephenm and @nutang 

Would you like to introduce yourselves to the Community?

Are there any gotchas or interesting things you've learnt about Vitis that would be good to share with the Community?

[stephenm]

Hey @sandrao . Sure, my name is Stephen. I have been in Xilinx for 13 years, mostly working on the embedded side of things. 

Creating a custom embedded Acceleration platform can seem like a daunting task, this is why I broke this into a series a blogs. The content in the blog is covered in the docs too. However, I wanted to break the overall task into their individual components. While creating the blog I discovered a few gothas along the way.

One of these gothas is that their needs to be at least two PFM.CLOCKS. This is also seen in the forum post by @_engineer :

https://forums.xilinx.com/t5/Vitis-Acceleration-SDAccel-SDSoC/Vitis-2020-1-Vector-Addition-example-is-not-working/m-p/1143930#M6767

This issue didnt manifest itself until deploying on the Hardware:

EXE: /usr/bin/xbutil
[XRT] ERROR: stoul
ERROR: xbutil program failed.

The fix here was to either manually modify the XCLBIN, or to update the HW component in the Platform to add the second PFM.CLOCK

Another thing I would recommend if creating a custom platform is to spend the few mins organizing the SW component files; such as the boot images, and kernel images.

The V++ packager will take all the files in your linux path (specified when creating the platform), and place these in the sd_card.img. I have seen some users that end up with a large

sd_card.img only to discover that it contained alot more images than they intended. I cover this in the blog below:

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Creating-an-Acceleration-Platform-for-Vitis-Part-Three-Packaging/ba-p/1138750

[evatrostaz]

Hi,

I'm struggling to make my zcu106 platform get recognized by Vitis as Embedded Acceleration.

https://forums.xilinx.com/t5/Vitis-Acceleration-SDAccel-SDSoC/Vitis-2019-2-ZCU106-Acceleration-platform-with-VCU/m-p/1149927#M6955

Base platform with just only Zynq MPSoC with Clocking wizard and Processor System Resets works fine, but after adding VCU (encode only) it's just not recognized as Acceleration platform :< Could this be some kind of bug?

[nutang]

Hi @sandrao 

My name is Nutan and I have 10 years of experience in the embedded domain.

I find two things very interesting about Vitis,

1. It provides prebuilt base platforms and common software components for Xilinx evaluation boards. Which helps users to get started quickly.

2. It allows users to customize their platform from hardware and software point of view and it also provides libraries which allow users to develop their prototype faster.

One of the gotchas is that while working on the Embedded Vision platform (former reVISION) for zcu104 stereovision example, I was facing a timing violation.

It is required to set the vivado switch at C/C++ build settings -> C/C++ Build -> Settings -> V++ Kernel Linker as shown below 

[hongh]

Continue with @nutang 's topic, when you have timing issue in the design, you can launch Vivado to explore the timing issue.

All the strategies of the synth/impl and parameters in Vivado can be passed to Vitis linker:

--vivado Options （--vivado.param/--vivado.prop）
https://www.xilinx.com/html_docs/xilinx2020_1/vitis_doc/vitiscommandcompiler.html?hl=--vivado

[stephenm]

@evatrostaz Welcome to the MTE. My name is Stephen. So, you can use the base design here:

https://www.xilinx.com/support/documentation/boards_and_kits/zcu106/2019_2/ug1250-zcu106-vcu-trd.pdf

Since the Vitis IDE is a unified tool that covers different personas; Data Center and Edge. You need to specify the intent of the platform. 

I cover this in the blog here:

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Creating-an-Acceleration-Platform-for-Vitis-Part-One-Creating/ba-p/1138208

In your case the intent should be

set_property platform.default_output_type "sd_card" [current_project]
set_property platform.design_intent.embedded "true" [current_project]
set_property platform.design_intent.server_managed "false" [current_project]
set_property platform.design_intent.external_host "false" [current_project]
set_property platform.design_intent.datacenter "false" [current_project]

 With respect to the PFM Interfaces. You dont need to use them all, you just need at least one so the Accelerated framework can be added. You need an interrupt and at least two clocks.

[sandrao]

Hi Team,

Another question from the @MomenJ  https://forums.xilinx.com/t5/Vitis-Acceleration-SDAccel-SDSoC/Generate-image-ub-from-Vitis-2019-2/td-p/1149947

[stephenm]

@MomenJ The image.ub is supplied in the Platform and is not generated in Vitis

Can you have a look at the blog here that discusses how to generate the sw components, including the image.ub for the platform:

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Creating-an-Acceleration-Platform-for-Vitis-Part-Two-Creating/ba-p/1138667

[nutang]

Hi @evatrostaz 

Have you referred the below platform?

https://github.com/Xilinx/Vitis_Embedded_Platform_Source/tree/2019.2/Xilinx_Official_Platforms/zcu104_vcu_ml

[evatrostaz]

@nutang 

Yes i did. I added AXI Interrupt Controller according to UG1393 / Ch.50 and VCU (PG252 / Ch.6) to working base Vitis acceleration platform.

@stephenm 

Already tried this solution but on 2019.2 version it's not working

[nutang]

Hi @sandrao , @stephenm @evatrostaz 

I have received a service request for this issue and I am working on it. 

[stephenm]

hey @freeze welcome to the MTE. Lets discuss your issue here:

https://forums.xilinx.com/t5/Vitis-Acceleration-SDAccel-SDSoC/XRT-Tid-140057287337920-ERROR-did-not-find-ddr-for-cuaddr-arg-0/td-p/1152042

First, lets introduce the xbutil utilitiy. This is a tool that can parse the xclbin file (XRT will also parse the xclbin):

https://www.xilinx.com/html_docs/xilinx2020_1/vitis_doc/xbutilutility.html

Can you try the dmatest here

[stephenm]

hey @vatistas welcome to the MTE. lets discuss your question:

https://forums.xilinx.com/t5/Vitis-Acceleration-SDAccel-SDSoC/Profiling-on-Vitis-with-custom-hw-platform-in-sw-emu-mode/td-p/1145390

Yes, Vitis Emulation is based on the powerful QEMU tool. Vitis supports SW Emu, and HW Emu. HW Emu emulates the PSU/PMU on QEMU and uses a Co-simulation with the Vivado simulator. However, since QEMU is not cyclic accurate, then the numbers presented in the analyser should be only used as guidance only.

To answer your questions. Once you have the build complete, select the run_summary

Launch the Vitis Analyser, and select Open Run Summary under PROFILE:

Navigate to the Run Summary:

[stephenm]

Another common issue is the XRT install seen here @Ormskirk

https://forums.xilinx.com/t5/Vitis-Acceleration-SDAccel-SDSoC/OpenCL-runtime-in-Vitis/td-p/1146883

UID: 1000
[Fri Sep 4 10:04:57 2020]
HOST: tim-virtualbox
EXE: /usr/bin/clinfo
[XRT] ERROR: XILINX_XRT must be set
[XRT] ERROR: XILINX_XRT must be set
[XRT] ERROR: XILINX_XRT must be set
Number of platforms 0

This specific issue looks like its on Alveo, but it equally pops up in edge too.

For edge, I covered this in the blog below:

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Creating-an-Acceleration-Platform-for-Vitis-Part-Three-Packaging/ba-p/1138750

For this particular issue. Can you follow the flow here:

https://www.xilinx.com/products/boards-and-kits/alveo/u200.html#gettingStarted

[patocarr]

Hi folks,

  I'd like to bring attention back to an issue in 2020.1 I've reported a few weeks back, and summarized in this post Petalinux-2020-1-vs-2019-2-QSPI-and-JTAG-boot 

  Perhaps related is this other post that shows Vitis importing a hardware platform and mischaracterizing it as Datacenter, when it should have been Embedded. The post is Vitis-2020-1-templates-missing-on-custom-xsa .

  Both cases are somehow related to having PS PCIe enabled in the design.

  Thanks to Stephen and Florent for handling this case. I would like to check on status.

Thanks,

-Pat

[stephenm]

@patocarr welcome to the MTE.

This was an interesting issue. So, for the benefit of other users. The issue you where seeing was that when you created a platform, and then subsequently tried to use this platform to create an app in Vitis. However, it was detected as a datacenter platform and thus the embedded template apps where not populated.

Normally, users can pass the intent via the Vivado project parameters. Unfortunatley in your case, this was a bug. I believe a CR was filed (ill double check).

The Workaround was to not actually generate the platform and to use the XS to create the project instead (this will actually create the platform automatically). This was you could use the embedded template apps. 

Have you had any success here? I had tried this with your XSA and I could create the embedded apps

[patocarr]

Hi,

  @stephenm I could get the embedded templates working with the workaround, however the created platform is still Datacenter. So only one app can be created this way.

  But the more serious issue is the related one, where the FSBL takes about 30 seconds to run. This happens with the Vitis generated FSBL as well as with Petalinux. The immediate side effect is programming the QSPI in Vivado and using the program_flash script both fail. Even booting the hardware takes this much longer. For now I've just disabled PS PCIe to keep developing the design, but soon enough this feature will be required.

  Appreciate the opportunity to ask the experts in the forum, as well as in XDF.

Thanks again folks,

-Pat

[freeze]

I am running in hardware emulation mode only...

[avv]

Hi,

I found a Vitis example of mixing RTL and C kernels (adders) that exchange data via DDR by designating data to be exchanged in the host code. I would like to see an example of mixing RTL and C kernels where kernel-to-kernel data is being passed without DDR (and its latency) by a streaming interface.

Second example I would like to see is two C kernels use similar kernel-to-kernel streaming interfaces. Current Vitis C example shows this only within a single kernel while OpenCL example shows kernel-to-kernel streaming.

Thank you.

avv