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Contributor
Contributor
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Registered: ‎03-03-2017

Multi-channel DMA or several DMAs

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I have implemented the firmware that captures the data from an external ADC, processes the data and stores it in the DDR using the AXI DMA. Due to the signal processing, I'm already using the 32 bits of the AXI bus. 

 

Now I have to replicate it for 4 simultaneous ADCs. I was wondering which is a better option, to use a multi-channel DMA (the four ADCs are connected to a single DMA using an AXI Interconnect module) or 4 different AXI DMAs? 

 

In the case of multi-channel DMA, is it possible to do it in polling mode?

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011
Now I have to replicate it for 4 simultaneous ADCs

Most likely this means you want to do 4 separate instances of DMA unless your sample rate on your ADCs is slow enough that they can be time muxed into a single multichannel DMA. The AXI DMA in multichannel mode uses one single AXI Stream interface and different channels are indicated by tid/tdest signals. You can use an AXI Stream Interconnect for the muxing.

www.xilinx.com

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011
Now I have to replicate it for 4 simultaneous ADCs

Most likely this means you want to do 4 separate instances of DMA unless your sample rate on your ADCs is slow enough that they can be time muxed into a single multichannel DMA. The AXI DMA in multichannel mode uses one single AXI Stream interface and different channels are indicated by tid/tdest signals. You can use an AXI Stream Interconnect for the muxing.

www.xilinx.com

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Visitor
Visitor
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Registered: ‎12-05-2017

If there is only one DDR memory, the MM data from 4 separate DMA engines would still have to be time muxed. Is this correct?

 

If there are 4 DDR memories for 4 ADCs, using multichannel DMA would not make sense, right? Thanks.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

This discussion is at the AXI DMA level.

 

Yes, you're right that everything will get 'scrambled' together on the other side of the AXI Interconnect and on the memory interface anyway, but that's not something you really need to worry about for the purposes of the original question. Which was about the front end and how to handle the multiple parallel streaming interfaces from the ADCs.

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Scholar
Scholar
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Registered: ‎06-10-2008

If you use a single DMA you have to be sure that every transaction you program will end within a limited time or else the other channels will be starved. If all 4 channels always produce a fixed amount of data in each frame time this should work (with a bit of buffering).

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Observer
Observer
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Registered: ‎08-01-2017

When we use multiple DMAs, how do we start all of them so that they work in parallel. Once I write the transfer size to the length register for one DMA, it starts the transfer and the baremetal application code blocks at this line until the interrupt is received and the interrupt handler is executed.

Xil_Out32(XPAR_AXI_DMA_0_BASEADDR + 0x28, 32);

This is the line of code where I write the length and start the transfer. Anything after this statement is executed only after the transfer is complete, interrupt occur and the interrupt handler code is run. Is there anyway that I can do this in a non-blocking way and start another DMA core immediately after I execute the above statement, without waiting for the interrupt to occur?

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Scholar
Scholar
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Registered: ‎06-10-2008

The only reason I can think of is bus starvation for the CPU. It needs to fetch the next instruction, but the bus is totally busy doing the DMA transfer. Doing a register write should NOT generate a wait.

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Registered: ‎03-24-2019

@bwiec , I confuse with the "multi-channel DMA" term used here.

"The AXI DMA in multichannel mode uses one single AXI Stream interface and different channels are indicated by tid/tdest signals." 

I think this is referring to the 1 DMA engine with using multichannel mode, and the data routed per tid/tdest signals, right?

--------------------------------------------------------------------------------

In Xilinx 7-Series DMA sub-system for PCIe, the DMA can be configured up to 4 physical Read (H2C) and 4 Write (C2H) Data Channels & each channel has a dedicated engine for H2C and C2H as well.

In this case, the multi-channel concept is different where each channel will has it own DMA engine.

Could you please help to clear my confusion?

 

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