11-27-2019 05:48 AM - edited 11-28-2019 01:10 AM
I am trying to accelerate a function on Vitis environment as I have done on SDSoC. However, v++ compiler is giving me error and the error is as the following:
ERROR: [CFGEN 83-2284] No stream resources found that can accomodate compute unit "decoder_top_1.INPUTDATA"
ERROR: [SYSTEM_LINK 82-36] [16:13:14] cfgen failed
ERROR: [SYSTEM_LINK 82-62] Error generating design file for (...)/cfgen_cfgraph.xml
ERROR: [SYSTEM_LINK 82-96] Error applying explicit connections to the system connectivity graph
ERROR: [SYSTEM_LINK 82-79] Unable to create system connectivity graph
I am stuck at this moment because I am not able to find similar issue on web. I observed this link : "https://forums.xilinx.com/t5/Alveo-Accelerator-Cards/Where-can-I-find-the-qdma-development-shell-for-Alveo-U200/m-p/991466#M310". It mentions about QDMA but I have neither SDAccel nor QDMA. Moreover, I am trying to use the application project of mine as I have done on SDSoC because Vitis should also support what I am doing on SDSoC. Do I have to download QDMA? Can't I run my Vitis application project without this QDMA? If i dont, what to do to get over this issue? Am i getting this since kernel and host cannot communicate? I guess the problem is sourced from Vivado. Compiling gives this error after Vivado is called and IP repository is loaded:
Note: I am sending some streaming data to the kernel, there is no issue about that.
Note: My vivado_hls.log file shows no error. I cannot see any other log file in my console.