Not able to debug multiprocessors design using Vitis (microblaze)
I have a weird problem where I cannot debug multiple microblaze processor on my Basys3 board (using a Artix7). I put this in Vitis but I also had the same problem while using Vivado 2017 with the SDK tool. I switch to the newest version in hope that would solve the issue but it did not. I do though prefer Vitis interface :).
Here is some context:
1. My Vivado design is like this: I have my top level in SystemVerilog that instanciates my 3 block design + my clock wizard to split my input clock for my 2 microblaze. My SV is attached.
4. My resulting debugging configuration looks like this:
5. Once I launch the debug, it gives my this error:
If I debug them alone it works fine but as soon as I put both, I get this error.
I did a lot of trials and searches on the net but now I'm out of ideas.
Is anybody was able to have a similar design to work?
Thank you very much in advance for the help!
PS: Important note though, I created a new project where I put my 2 processors in the same block design with the MDM also in the same block design. By doing it like that, it was working fine. It seems it is an issue with multiple processor on different design blocks while connecting them with a MDM external to their block design.