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Contributor
Contributor
760 Views
Registered: ‎07-23-2019

Peer 2 peer transfer using xilinx FPGA

Hi,

I am looking for solution to transfer data from one or more Xilinx PCIe device(PCIe edge connector card) to other (U.2 NVMe form factor) over PCIe switch.

Based on my understanding Xilinx Alevo based card with SDAccelCL support this feature but SDAcclCL does not support this fature for third part hardware. 

Does xilinx support this feature for PCIe End point implemented on Alevo or it require NVMe (CMB) feature implemented in Alevo card?

Is p2pdma kernel fature support for Xilinx PCIe EP/ NVMe HA IP or it require additional feature to support P2P transfer.

 

Thanks.

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Xilinx Employee
Xilinx Employee
686 Views
Registered: ‎06-04-2018

Hi @rkvr ,

You can find the following p2p designs for your reference(FPGA <-> NVMe SSD)

1. P2P Simple -- Highlight Simple P2P Read/Write operations

https://gitenterprise.xilinx.com/SDxGitExamples/Vitis_Accel_Examples/tree/master/host/p2p_simple

2. P2P Bandwidth -- Highlight the throughput for Synchronous and Asynchronous P2P operations

https://gitenterprise.xilinx.com/SDxGitExamples/Vitis_Accel_Examples/tree/master/host/p2p_bandwidth

 

Regards,
Vishnu
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Contributor
Contributor
670 Views
Registered: ‎07-23-2019

I am not able to access shared link
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Contributor
Contributor
625 Views
Registered: ‎07-23-2019

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Adventurer
Adventurer
342 Views
Registered: ‎05-29-2018

Hi @bchebrol @rkvr and all,

I would like to use the same examples, but as far I can see from the README of the two github links provided, all of the Alveo boards are excluded:

<< Platforms containing following strings in their names are not supported for this example :

zc
_u25_
u200
u250
u280
u50
vck
aws

>>

 

On the other side, from this page, U200 and U280 are clearly shown as usable in this configuration:

 https://xilinx.github.io/XRT/master/html/p2p.html

 

So, why the provided examples should not work on the Alveo boards?
Do they have to be modified to work on these devices?
And if it is the case, what should be changed?

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Xilinx Employee
Xilinx Employee
325 Views
Registered: ‎06-04-2018

Hi @ecalore,

The designs are supported only for samsung platform where the transfer is between FPGA<->Smart SSD

Regards,
Vishnu
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Adventurer
Adventurer
307 Views
Registered: ‎05-29-2018

Hi @bchebrol ,

thanks for the prompt answer.

Just for clarity... you mean that the linked examples on the Xilinx GitHub are meant to be used just for a specific samsung platform, but it is possible to implement a different code performing what is shown at this link, using an Alveo board and a generic PCIe connected NVMe SSD:

https://xilinx.github.io/XRT/master/html/p2p.html

Right?

Thanks in advance.

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Xilinx Employee
Xilinx Employee
269 Views
Registered: ‎06-04-2018

Hi @ecalore,

The designs that are shared(p2p_simple, p2p_bandwidth) can be used for all versions of samsung platforms.

If you are looking for P2P between FPGA<->FPGA you can refer the following design : 

https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/host/p2p_fpga2fpga

Regards,
Vishnu
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Adventurer
Adventurer
213 Views
Registered: ‎05-29-2018

Hi @bchebrol ,

thanks for the link, I am actually looking for FPGA<->NVMe, but I think I can start from that example.

Sorry to bother you again, but I have another question:

from this document it seems that there is no P2P support for Alveo U50 boards (according to Table 6, Page 12):

https://www.xilinx.com/support/documentation/boards_and_kits/accelerator-cards/ug1120-alveo-platforms.pdf

but I noticed that two days ago the picture at this link has been updated and now it depicts also a couple of U50 boards (one of each performing P2P with an NVMe, which is exactly what I am trying to do):

https://xilinx.github.io/XRT/master/html/p2p.html

Consequently, which document is the correct one?

Does the Alveo U50 support P2P? And if it is the case, which Platform should I use if the ones in Tab.6 of UG1120 are not supporting it?

 

Thanks in advance.

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Xilinx Employee
Xilinx Employee
186 Views
Registered: ‎06-04-2018

Hi @ecalore ,

The documentation is targeting 2020.1 release. Now we are planning to support U50 platform in the coming release. I guess you can target the following U50 card which support P2P. xilinx_u50_gen3x16_xdma_base_4

Thanks,

Vishnu

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