07-20-2021 10:34 AM
I am running an RTL kernel with 12 memory interfaces for 12 banks in HBM using the Vitis accelerated flow. Upon running the code, I find the execution is stuck during the Programing creation process. In other words, for the code below:
It outputs the statement 'before' but not 'after'. There is no timing violations and the build process was completed successfully.
while running the dmesg -wH command , I find the below logs:
Not sure what it exactly means. Also, I am finding that the kernel (.xclbin) is being flashed onto the card with status (START) for the desired compute unit. Usually, I find this status as (IDLE).
The other observation is that, once I terminate the current program and run it again, I find the below error:
with dmeg output:
What could be the possible reason for such error.
07-21-2021 12:35 AM
Does the example design work fine on the platform? What‘s your platform version?
07-21-2021 06:31 AM
Yes , the example designs work fine.Infact, the program was initially running fine with 10 memory interfaces connected to HBM. I had later used 2 more and connected them with DDR and faced this issue. I initially suspected the cause to be some mismatch settings of the kernel parameters for DDR like data line width or parameters setting like wrong burst length. But, facing the same issue with 12 HBMs also.
The board I use is Alveo U280 and Vitis version 2019.2