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jyerra2
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Registered: ‎11-01-2017

RTL Kernel Communication between Kernels using AXI interfaces

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Hi,

 

I have been trying to understand data transfer methodologies between the host and the device and I think I understand them to an extent. The host code needs to create read/write buffers on the DDR banks of the board and the device kernels use AXI interfaces to interact with these buffers and read from/write into these buffers whose pointers can be accessed by the host code as well. I am editing the Makefile with LDCL_FLAGS <kernel_name>.<AXI_IF_name>:<bank_name> --sp in order to make connections between the kernels and the DDR banks. Am I on the right track?

 

However, I am not sure how we can directly connect AXI interfaces such that we can enable two RTL kernels to directly talk to each other. While using RTL Kernels, I am using the RTL Kernel Wizard to generate the AXI interfaces. However, while using OpenCL kernels, how do we specify AXI interfaces and instantiate them?

 

Thank you for your patience!

 

Sincerely,

Janish Yerra

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evant
Xilinx Employee
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Registered: ‎09-08-2011

The best github example for you likely is this one: https://github.com/Xilinx/SDAccel_Examples/tree/master/getting_started/rtl_kernel/rtl_adder_pipes

 

It's for passing information between three RTL kernels using pipes. It would be the general flow to follow, there is another example on how to mix rtl and openCL kernels via the same pipe method which is why that would be the best choice.

If at first you don't succeed, try redefining success?

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evant
Xilinx Employee
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Registered: ‎09-08-2011

the device kernels use AXI interfaces to interact with these buffers and read from/write into these buffers whose pointers can be accessed by the host code as well. I am editing the Makefile with LDCL_FLAGS <kernel_name>.<AXI_IF_name>:<bank_name> --sp in order to make connections between the kernels and the DDR banks. Am I on the right track?

 

This seems valid, depending what you are trying to do. You can do this to map kernels to banks.

 

However, I am not sure how we can directly connect AXI interfaces such that we can enable two RTL kernels to directly talk to each other. While using RTL Kernels, I am using the RTL Kernel Wizard to generate the AXI interfaces. However, while using OpenCL kernels, how do we specify AXI interfaces and instantiate them?

 

When you use an openCL kernel, you should be using pipes to have direct communication between kernels. The axi interface in the RTL kernel is because that is how the actual HDL code interacts with the memory controllers, but for C++ and openCL that is intended to be abstracted away for you.

 

 

If at first you don't succeed, try redefining success?
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jyerra2
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Registered: ‎11-01-2017

Yes, I will be working mostly with RTL Kernels, therefore, I wanted to understand how to enable communication between two kernels. 

 

I am following the RTL Kernel examples on GitHub. Would those suffice to understand how to use the AXI interfaces efficiently?

 

SIncerely,

Janish Yerra

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evant
Xilinx Employee
Xilinx Employee
1,937 Views
Registered: ‎09-08-2011

The best github example for you likely is this one: https://github.com/Xilinx/SDAccel_Examples/tree/master/getting_started/rtl_kernel/rtl_adder_pipes

 

It's for passing information between three RTL kernels using pipes. It would be the general flow to follow, there is another example on how to mix rtl and openCL kernels via the same pipe method which is why that would be the best choice.

If at first you don't succeed, try redefining success?

View solution in original post

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cchuvalas
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Registered: ‎09-12-2018
I have a similar, but different question in this post:
https://forums.xilinx.com/t5/Implementation/opencl-RTL-kernel-with-multiple-axi-interfaces/m-p/963576#M24306
If you could check it out, that would be appreciated.
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