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Explorer
Explorer
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Registered: ‎05-23-2017

Re: array partitioning: long runtime and suboptimal QoR due to large multiplexers

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@nupurs

Thanks for your reply.

I checked vivado_hls.log file and didn't find the II number for using unrolling. The compilation takes a very long time(at least 14 hours).

INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'read_query_or'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111]  Elapsed time: 1158.04 seconds; current allocated memory: 3.672 GB.
INFO: [HLS 200-434] Only 0 loops out of a total 1 loops have been pipelined in this design.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111]  Elapsed time: 1803.52 seconds; current allocated memory: 243.396 MB.

And I just found it stoped at linking stage and compalined with a error.

Here is the output from the terminal and _x/link/vivado/vivado.log:

2323.jpg

ddd.jpg

But didn't find any useful information.

Could the previous warning cause this error?

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Explorer
Explorer
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Registered: ‎05-23-2017

Finally I found this issue is caused by the partionning and unroll of large size of array

View solution in original post

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Moderator
Moderator
902 Views
Registered: ‎06-24-2015

@mathmaxsean

 

It seems you are using SDAccel. Hence I am moving this to SDAccel board.

Thanks,
Nupur
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Advisor
Advisor
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Registered: ‎04-26-2015

@mathmaxsean You haven't actually told us anything about your project, but that warning is normally a bad sign. If you've got a very large fully-partitioned array that's being accessed one element at a time, that can take an extremely large amount of hardware - which then results in problems when the tools try to build the design.

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Explorer
Explorer
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Registered: ‎05-23-2017

@u4223374

Thanks.

Is there a way that I can send the project to you. The size of the project is large.

Thanks.

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Advisor
Advisor
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Registered: ‎04-26-2015

@mathmaxsean There's no point sending the project to me since I don't have SDAccel; my experience with this comes from HLS, which is the tool underlying much of SDAccel's FPGA-side functionality. However, if you post the code here then lots of people can have a look at it. It's unlikely that your C code is very large.

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Highlighted
Explorer
Explorer
811 Views
Registered: ‎05-23-2017

Finally I found this issue is caused by the partionning and unroll of large size of array

View solution in original post

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