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teraser
Participant
Participant
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Registered: ‎11-18-2010

Regular PR Expanded PR with SSI devices

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Hello SDAccel Team,

 

ug1164, page8, Understanding Regular and Expanded PR Hardware Platforms says:

"The XPR method is ... used with SSI devices."

 

Can I use regular PR with SSI?

 

Best wishes,

Victor

--
Dies diem docet.
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dalthoff
Xilinx Employee
Xilinx Employee
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Registered: ‎06-07-2016

Hi @teraser,

 

In UG1234 there is a section on this, check out page 11.

 

Routability issues are most likely occur when you have large kernels and limited space to physically route the signals around static regions and across SLR boundaries.

 

The XPR flow will allow the non-base region i.e. memory interfaces, etc. to be rerouted when the OpenCL region is routed to a more optimal path so critical timing paths can be met. This limits the non-reroutable static region to ~8% of the device.  

 

The non-XPR flow will not re-route the memory interfaces, etc. resulting in a non-reroutable region of, for example, ~30% on a KU115 with 4 DDR controllers. 

 

In non-XPR platforms with high resource utilization, the router may not be physically able to route demanding designs across the SLR boundary where space is limited.

 

 

The case where a kernel would not need access across the SLR boundary is limited to kernels that do not need the DMA Subsystem for PCIe, basic control interfaces, and clock sources, which is extremely limited. 

 

If you are using 2 DDR interfaces instead of 4 the static region in a non-XPR platform might be more manageable. And with careful floorplanning you may not have routability issues if the kernels occupy less than 80% of the programmable region.

 

Best

-Dutch

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dalthoff
Xilinx Employee
Xilinx Employee
3,563 Views
Registered: ‎06-07-2016

Hi @teraser

 

You can use the PR method with SSI devices.

 

Note, the PR method will limit the max frequency of the kernel due to routeability issues. 

 

Best,

-Dutch

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teraser
Participant
Participant
3,513 Views
Registered: ‎11-18-2010

Hi @dalthoff,

 

Can you describe these issues (or point me to the document where I can read it)?

 

If I will have two kernels in two SLRs, not crossing SLR border will I have the routability issues?

 

Best wishes,

Victor

--
Dies diem docet.
0 Kudos
dalthoff
Xilinx Employee
Xilinx Employee
6,116 Views
Registered: ‎06-07-2016

Hi @teraser,

 

In UG1234 there is a section on this, check out page 11.

 

Routability issues are most likely occur when you have large kernels and limited space to physically route the signals around static regions and across SLR boundaries.

 

The XPR flow will allow the non-base region i.e. memory interfaces, etc. to be rerouted when the OpenCL region is routed to a more optimal path so critical timing paths can be met. This limits the non-reroutable static region to ~8% of the device.  

 

The non-XPR flow will not re-route the memory interfaces, etc. resulting in a non-reroutable region of, for example, ~30% on a KU115 with 4 DDR controllers. 

 

In non-XPR platforms with high resource utilization, the router may not be physically able to route demanding designs across the SLR boundary where space is limited.

 

 

The case where a kernel would not need access across the SLR boundary is limited to kernels that do not need the DMA Subsystem for PCIe, basic control interfaces, and clock sources, which is extremely limited. 

 

If you are using 2 DDR interfaces instead of 4 the static region in a non-XPR platform might be more manageable. And with careful floorplanning you may not have routability issues if the kernels occupy less than 80% of the programmable region.

 

Best

-Dutch

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