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sream
Observer
Observer
3,061 Views
Registered: ‎03-16-2017

Runtime data transfers between FPGA and CPU

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Hi,

It is very clear that SDAccel generates the hardware of OpenCL Implementation, and the same can be uploaded to FPGA.

 

But how to transfer the data between FPGA and CPU while run time? If there are any examples and documentation for data transfers between FPGA and CPU (using PCIe), can you please share them?

 

 

 

Best Regards,

Sreehari A.

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heeran
Xilinx Employee
Xilinx Employee
4,662 Views
Registered: ‎07-18-2014

I think currently host can only read/write data from/to Global Memory(DDR). 

 

I think you can refer below example if you need to repetitively wants to send the data:

https://github.com/Xilinx/SDAccel_Examples/tree/master/getting_started/host/overlap_ocl

 

 

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heeran
Xilinx Employee
Xilinx Employee
3,057 Views
Registered: ‎07-18-2014

hey @sream,

We have one example specific to data_transfer, which shows various way of data movements between host (Cpu) and Device(FPGA):

https://github.com/Xilinx/SDAccel_Examples/tree/master/getting_started/host/data_transfer_ocl

 

There are list of examples which are related host code:

https://github.com/Xilinx/SDAccel_Examples/tree/master/getting_started/host

 

-Heera

 

 

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sream
Observer
Observer
2,930 Views
Registered: ‎03-16-2017

Thank you very much for the good examples Heera.

I have still some doubts and confusions here.

SDAccel generates the  .xclbin (hardware) file in order to deploy in the FPGA.

Is the .xclbin represents the kernel code along with data ports between host and device?

"What and how If I wanted to send the different data repetitively to the FPGA from CPU and do some data process through the .xclbin and back the result?"

How should I connect data ports through .xclbin from CPU?

Is it related to multi kernels concepts?

 

Thanks in advance.

 

Best Regards,

Sreehari.

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sream
Observer
Observer
2,880 Views
Registered: ‎03-16-2017

Hello Heera,

Can you please suggest me about how to transfer data to device (FPGA) and compute on kernel and get result back to host "repetitively"?

 

Should I use streams for this?

 

 

 

Best Regards,

Sreehari.

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heeran
Xilinx Employee
Xilinx Employee
4,663 Views
Registered: ‎07-18-2014

I think currently host can only read/write data from/to Global Memory(DDR). 

 

I think you can refer below example if you need to repetitively wants to send the data:

https://github.com/Xilinx/SDAccel_Examples/tree/master/getting_started/host/overlap_ocl

 

 

View solution in original post

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