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823 Views
Registered: ‎07-30-2018

SDLAccel RTL Kernel with slave AXI4 port

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Hi All,

 

I'm porting an existing accellerator card IP core into the SDAccel enviroment.

The issue that I have is that it has a salve AXI4-MM interface for a data port that needs to be conected to the PCIe XDMA engine.It also has an AXI4-MM interface for conection to external memory and hte IP core controles the DDR4 data transfers. The PCIe XDMA is a streaming data interface for a number of job descriptors which a max size of 16K each;

 

I Know that the docs state that all AXI4 interfaces should be masters or streaming, howrver it also implies that an AXI4-MM SLAVE can be used.

 

Has anyone ever done this or know if it is possible. The target platform is theVCU1525 card with default DSA setup, although this may need modifications.

 

Can anyone provide any help with this

 

Thanks

 

Mark N

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Registered: ‎07-30-2018

回复: SDLAccel RTL Kernel with slave AXI4 port

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Iris

 

Thanks, so all I need to do is the inclusion of the SRL interconnects on the AXI4 memory mapped interface from the XDAM.

 

This is exactly what I was hoping for.

 

Thanks

 

Mark

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

回复: SDLAccel RTL Kernel with slave AXI4 port

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Mark,

XDMA IP should have Memory Map Interface used as Master port  which can connect with your slave port

regards

Iris

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Highlighted
914 Views
Registered: ‎07-30-2018

回复: SDLAccel RTL Kernel with slave AXI4 port

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Iris

 

Thanks, so all I need to do is the inclusion of the SRL interconnects on the AXI4 memory mapped interface from the XDAM.

 

This is exactly what I was hoping for.

 

Thanks

 

Mark

View solution in original post

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Participant
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Registered: ‎01-27-2019

回复: SDLAccel RTL Kernel with slave AXI4 port

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Hi! @mnoble-titanic, I may meet the same problem with you when generating RTL Kernel. I have four AXI MM ports and one AXI DMA slave ports in my design. I also don't know how to process this AXI DMA slave port. I want to ask what do you mean about the inclusion of the SRL interconnects on the AXI4 memory mapped interface from XDMA. Thx!

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