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Observer
Observer
6,336 Views
Registered: ‎10-26-2015

SDSOC Platform with XADC

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I am trying to create an SDSOC platform with XADC included on a Digilent Zybo Zynq (Zc701) board. I have followed Adam Taylor's MicroZed Chronicles, so far I have a Vivado design with XADC included which works fine, it displays the internal temperature over UART. Now I am trying to create an SDSOC platform following part 108 of Adam's blog. He uses Sdsoc 2015, but I am using SDSOC 2016.2.

How do I convert these 6 properties to SDSoc 2016.2

 

set_param project.enablePlatformHandoff true;
set_property SDSOC_PFM.CLOCK_ID 0 [get_bd_pins /processing_system7_0/FCLK_CLK0];
set_property SDSOC_PFM.MARK_SDSOC true [get_bd_pins /processing_system7_0/FCLK_CLK0];
set_property SDSOC_PFM.MARK_SDSOC true [get_bd_pins /rst_processing_system7_0_100M/interconnect_aresetn];
set_property SDSOC_PFM.MARK_SDSOC true [get_bd_pins /rst_processing_system7_0_100M/peripheral_aresetn];
set_property SDSOC_PFM.MARK_SDSOC true [get_bd_pins /rst_processing_system7_0_100M/peripheral_reset];

I have read UG1146 2016.2 edition and this is what I have come up with

 

source -notrace F:/Xilinx/SDSoC/2016.2/scripts/vivado/sdsoc_pfm.tcl
sdsoc::create_pfm Fir_hw.pfm
set pfm [sdsoc::create_pfm Fir_hw.pfm]
sdsoc::pfm_name $pfm "Xilinx" "xd" "zc701" "1.0"
sdsoc::pfm_description $pfm "Zynq ZC701 Board"
sdsoc::pfm_clock $pfm FCLK_CLK0 processing_system7_0 0 true rst_processing_system7_0_100M
sdsoc::pfm_axi_port $pfm M_AXI_GP0 processing_system7_0 M_AXI_GP

Is this correct?. I want to use the XADC in SDSOC, and then eventually program an FIR filter first in PS, and then in PL comparing their performances

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Xilinx Employee
Xilinx Employee
11,465 Views
Registered: ‎06-29-2015

Hi zer0c00l,

 

This platform looks very similar to the zc702_led example platform that also has a PS accessed AXI-Lite slave (in that case its a GPIO, but still similar accessing interface to the XADC). Check out the UG1146 Example: Software Control of Platform IP starting on page 47 (2016.2 version http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug1146-sdsoc-platforms-and-libraries.pdf). This guide walks you though step-by-step in creating a platform including the tcl commands.

 

Hope that helps.

Sam

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Observer
Observer
6,331 Views
Registered: ‎10-26-2015

Here is my Vivado design (also 2016.2)vivado design.png

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Xilinx Employee
Xilinx Employee
11,466 Views
Registered: ‎06-29-2015

Hi zer0c00l,

 

This platform looks very similar to the zc702_led example platform that also has a PS accessed AXI-Lite slave (in that case its a GPIO, but still similar accessing interface to the XADC). Check out the UG1146 Example: Software Control of Platform IP starting on page 47 (2016.2 version http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug1146-sdsoc-platforms-and-libraries.pdf). This guide walks you though step-by-step in creating a platform including the tcl commands.

 

Hope that helps.

Sam

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Visitor
Visitor
6,168 Views
Registered: ‎06-26-2016

Hi,

I have the same problem but i use Red Pitaya Board which has the same FPGA like Zybo. Red pitaya has 4 Analog Interfaces(2 Inputs and 2 Outputs). I would like to generate a signal and to send it out with XADC. I use Linux and i generated all the boot files. But i dont know what should i do to generate the files into "arm-xilinx-linux-gnueabi" the header file and the static library.
Can i use the same files in zc702_led?

Maybe i should use the C-Callable libraries, but i think it is complicated. Is there any anthor way to solve my problem.

Is there any samples or any examples can help me.

 

Thank you

Issam

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